An efficient, unified algorithm, Advanced Two-Phase Cluster Partitioning, is proposed for automated synthesis
of pseudo-exhaustive test generator for Built-In Self-Test (BIST) design. A prototype of the algorithm, Two-Phase Cluster Partitioning, has been proposed and the hierarchical design procedure is computationally efficient
and produces test generation circuitry with low hardware overhead. However, in certain worst case, the algorithm
may generate a sub-optimal design which requires more test patterns and/or hardware overhead. In order to
generate a globally optimal design, further improvement of two-phase algorithm can be achieved by expanding
the design space for the formation of linear sum so that the number of test signals required for pseudo-exhaustive
testing can be reduced. We demonstrate the effectiveness of our approach by presenting detailed comparisons of
our results against those that would be obtained by existing techniques.

Chien-In Henry Chen

Partitioning Techniques for Built-In Self-Test Design

In this paper we provide a distributed solution to perform Design Rule Checking (DRC) of a layout by exploitingeither spatial independence or layer independence in layout data. We show that the former approach to DRCcan result in reasonable speedup only for large layouts, whereas, the latter approach shows a better performancefor smaller layouts. We also provide an algorithm to optimally partition a layout and a scheme to allocate DRCtasks to idle processors in a Distributed Computing Environment (DCE) to attain load balancing.

S. K. Nandy

Geometric Design Rule Check of VLSI Layouts inDistributed Computing Environment

We present in this paper a linear time optimal algorithm for minimizing the density of a channel (with exits) bypermuting the terminals on the two sides of the channel. This compares favorably with the previously knownnear-optimal algorithm presented in [6] that runs in superlinear time. Our algorithm has important applicationsin hierarchical layout design of intergrated circuits. We also show that the problem of minimizing wire length bypermuting terminals is NP-hard in the strong sense.

Yang  Cai

D. F. Wong

Jason  Cong

Channel Density Minimization by Pin Permutation

Design Rule Checking is a compute-intensive VLSI CAD tool. In this paper we propose a parallel algorithm to perform Design Rule Check (DRC) of Layout geometries in a VLSI layout. The algorithm assumes the parallel architecture to be a two-dimensional mesh of processors. The algorithm is based on a linear quadtree representation of the layout. Through a complexity analysis it is shown that it is possible to achieve a linear speedup in DRC with respect to the number of processors.

R. B. Panwar

Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors

We discuss a new minimum density objective for spanning and Steiner tree constructions. This formulation ismotivated by the minimum-area layout objective, which is best achieved through balancing the usage of horizontaland vertical routing resources. We present two efficient heuristics for constructing low-density spanning trees andprove that their outputs are on average within small constants of optimal with respect to both tree cost anddensity. Our proof techniques suggest a non-uniform lower bound schema which can afford tighter estimates ofsolution quality for a given problem instance. Furthermore, the minimum density objective can be transparentlycombined with a number of previous interconnection objectives (e.g., minimizing tree radius or skew) withoutaffecting solution quality with respect to these previous metrics. Extensive simulation results suggest that applicationsto VLSI global routing are promising.

C. J. Alpert

J.  Cong

A. B. Kahng

G.  Robins

M.  Sarrafzadeh

On the Minimum Density Interconnection TreeProblem

We first present a parallel algorithm for finding the optimal implementations for the modules of a slicing floorplanthat respects a given slicing tree. The algorithm runs in O(n) time and requires O(n) processors, where n is thenumber of modules. It is based on a new O(n2) sequential algorithm for solving the above problem. We thenpresent a parallel algorithm for finding a set of optimal implementations for a slicing floorplan whose correspondingslicing tree has height O(logn). This algorithm runs in O(n) time using O(logn) processors. Our parallel algorithmsdo not need shared memory and can be implemented in a distributed system.

Cheng-Hsi  Chen

Ioannis G. Tollis

Area Optimization of Slicing Floorplans in Parallel

This paper describes an expert system for Hardware Synthesis. Details of the target digital system are input tothe expert system using Very High Speed Integrated Circuit Hardware Description Language (VHDL). TheVHDL representation is first translated to a knowledge representation scheme known as a &#8216;hologram&#8217; which is acombination of rule, frame and semantic network representation schemes. The hologram representation of thetarget system is then input to the inference engine, which matches the target system to the Knowledge Basecomponents and selects an appropriate set for implementation, and connects them creating a digital circuit. Somedesign examples are described. The expert system approach results in designs very close to designs from a humandesigner. In its present form, the system does not perform a design space exploration for alternate designs, butexpects the designer to alter the VHDL representation, after observing the results from previous design cycles.

Sajjan G. Shiva

Judit U. Jones

A VHDL Based Expert System for HardwareSynthesis

Rectangular dualisation is a technique used to generate rectangular topologies for use in top-down floorplanning
of integrated circuits. In order for this technique to be used in a floorplanning system, its input, the connectivity
graph representing an integrated circuit has to fulfill a number of conditions. This paper presents an efficient
algorithm that transforms an arbitrary connected graph, representing an integrated circuit, into another graph
that is guaranteed to fulfill these conditions and to admit rectangular duals. Effectively, the algorithm solves the
global routing problem by using three techniques: passthrough, wiring blocks and collapsed wiring blocks. Resulting
floorplans may be passed to a chip assembler and detailed router package to complete the layout. This paper also
introduces a novel technique to transform a tree of biconnected sub-graphs into a block neighbourhood graph
that is a path.

Marwan A. Jabri

Building Rectangular Floorplans–A Graph
Theoretical Approach

In this paper, we present a novel concept of the general connectivity among cells. While conventional conceptconsiders direct connections only, the new concept considers both the direct and indirect connections among cellsleading to a model capturing a more precise relationship among cells. Based on the model, a new parallel clusteringapproach is proposed and analyzed. Another new concept of the stable cluster is introduced to improve theclustering result. In conjunction with the clustering process, an investigatory procedure which back tracks thecluster development process to check if all clusters are stable is also developed. Initial test runs, using the newclustering approach for placement, yield an encouraging 21.6% reduction on the number of feed-throughs in acomplex ASIC design.

Wenjun  Zhuang

Yong Ching Lim

Ganesh  Samudra

Neng  Yan

A New Clustering Method Based onGeneral Connectivity

We present an effective solution to the linear placement problem, which has several applications in the physicaldesign of integrated circuits. Our approach belongs to the class of iterative improvement heuristics. The importantdifference of this new technique from the previous ones is in its moves, and in the order of application of thesemoves. A phase of the algorithm begins with simple moves and gradually shifts towards more complex moves.Phases are repeated as long as further improvement is possible. Our experimental results show that nearly optimalsolutions can be achieved. For a number of examples collected from the literature, our algorithm generatedoptimal solutions.

Youssef  Saab

Cheng-Hua  Chen

An Effective Solution to the LinearPlacement Problem

In this paper, we discuss the use of parallel discrete event simulation (PDES) algorithms for execution of hardwaremodels written in VHDL. We survey central event queue, conservative distributed and optimistic distributedPDES algorithms, and discuss aspects of the semantics of VHDL and VHDL-92 that affect the use of thesealgorithms in a VHDL simulator. Next, we describe an experiment performed as part of the Vsim Project at theUniversity of Adelaide, in which a simulation kernel using the central event queue algorithm was developed. Wepresent measurements taken from this kernel simulating some benchmark models. It appears that this technique,which is relatively simple to implement, is suitable for use on small scale multiprocessors (such as current desktopmultiprocessor workstations), simulating behavioral and register transfer level models. However, the degree ofuseful parallelism achievable on gate level models with this technique appears to be limited.

Peter J. Ashenden

Henry  Detmold

Wayne S. McKeen

Execution of VHDL Models Using Parallel DiscreteEvent Simulation Algorithms

About this journal

Journal profile

Meet the editorial board

Editor spotlight

Submit your proposal

Do you think there is an emerging area of research that really needs to be highlighted? Or an existing research area that has been overlooked or would benefit from deeper investigation? Raise the profile of a research area by leading a Special Issue.

VLSI Design