The use of associative memories&#8212;storage devices that allow data retrieval based on contents&#8212;has often beensuggested to speed up the performance of many applications. Until recently, using such content-addressablememories (CAMs) was unfeasible due to their high hardware cost. However, the advent of VLSI has made theclass of fully-parallel associative memory cost-effective for implementation. This paper briefly overviews designof several fully parallel associative memories proposed in the literature, concentrating on the design of fully-parallel&#952;-search CAMs.Existing market realities require that product development be fast and predictable. As a result, design flexibilityand automation are becoming increasingly important design features. Using the various CAM designs reviewed,the paper collects the features of these designs into a general, modular CAM organization and describes its majorcomponents. The modular CAM organization can be used to design application specific CAMs of varying degreesof functionality. Design and space complexity of a sample associative memory suitable for relational databaseoperations is studied. Finally, the application of genetic algorithms as a means to developing automated designtools for fabrication of modular VLSI design chips is discussed.Given a library of CAM modules, the desired functionality and a set of speed and area constraints, thisoptimization technique produces a suitable CAM design. The proposed technique has been implemented and itsperformance measure is briefly addressed.

A. R. Hurson

S.  Pakzad

Modular Scheme for Designing Special PurposeAssociative Memories and Beyond

Rochit   Rajsuman

Special Issue on Digital Hardware Testing

The high degree of parallelism in the simulation of digital VLSI systems can be utilized by a data flow architecture
to reduce the enormous simulation times. The existing logic simulation accelerators based on the data flow principle
use a static data flow architecture along with a timing wheel mechanism to implement the event driven simulation
algorithm. The drawback in this approach is that the timing wheel becomes a bottleneck to high simulation
throughput. Other shortcomings of the existing architecture are the high communication overhead in the arbitration
and distribution networks, and reduced pipelining due to a static data flow architecture. To overcome these, three
major improvements are made to the design of a classical data flow based logic simulation accelerator. These
include:1) A novel and efficient technique for implementing a pseudo-dynamic data flow architecture to increase
pipelining.2) Implementation of a modified distributed event driven simulation algorithm.3) Localized processors for fast evaluation of small primitives.

A. Mahmood

J. Herath

J. Jayasumana

An Improved Data Flow Architecture for Logic
Simulation Acceleration

In this paper, we present a Simulated Evolution Gate Matrix layout Algorithm (SEGMA) for synthesizing CMOS
random logic modules. The gate-matrix layout problem is solved as a one-dimensional transistor gates placement
problem. Given a placement of all the transistor gates, simulated evolution offers a systematic method to improve
the quality of the layout that is measured by the number of tracks needed for the given netlist. This is accomplished
by identifying a subset of gates whose relative placements are deemed “poor quality” according to a heuristic
criterion. By rearranging the placement of these identified subsets of gates, it is hoped that a gate placement with
better quality, meaning fewer tracks, may emerge. Since this method enables the current “generation” of gate
placement to evolve into a more advanced one in a way similar to the biological evolution process, this method
is called simulated evolution. To apply simulated evolution to solve the gate-matrix layout problem, we propose
a novel heuristic criterion, called randomized quality factor, which facilitates the judicious selection of the subset
of poor quality gates. Several carefully devised and tested strategies are also implemented. Extensive simulation
results indicate that SEGMA is producing very compact gate-matrix layouts.

Chi-Yu Mao

Yu   Hen Hu

SEGMA: A Simulated Evolution Gate-Matrix Layout
Algorithm

This paper describes a Prolog based Block Extraction System (ProBES) which converts a transistor level descriptionof a CMOS circuit into a logic block level description. The operation of ProBES is conceptually similar to thatof a circuit extractor. However, whereas a circuit extractor is used to identify circuit primitives such as transistors,resistors and capacitors from the geometrical information in a mask level layout description, ProBES can be usedto identify predefined gates and logic blocks in a CMOS transistor network. ProBES operates according to thecircuit hierarchy. Basic gates such as inverters, transmission-gates, nands, nors, etc. are identified first. Logicblocks composed of these gates are then identified. More complex blocks which contain blocks already identifiedare recognized next and so on. ProBES is meant to be used as an aid in the verification of logic design. It canprovide a connectivity check for a circuit.

Inderpreet  Bhasin

Joseph G. Tront

Block-Level Logic Extraction from CMOS VLSILayouts

We present a new approach to the problem of register-transfer level design optimization of pipelined data paths.The output of high level synthesis procedures, such as Sehwa, consists of a schedule of operations into time steps,and a fixed set of hardware operators. In order to obtain a register-transfer level design, we must assign operationsto specific operators, values to registers, and finish the interconnections. We first perform module assignmentwith the goal of minimizing the interconnect requirements between RT-level components as a preprocessingprocedure to the RT-level design. This will result in a smaller netlist which makes the design more compact andthe design process more efficient. In addition to reducing the total number of interconnects, this approach willalso reduce the total number of multiplexors in the design by eliminating unnecessary multiplexing at the inputsof shared modules. The interconnect sharing task is modeled as a constrained clique partitioning problem. Wedeveloped a fast and efficient polynomial time heuristic procedure to solve this problem. This procedure is 30&#8211;50 times faster than other existing heuristics while still producing better results for our purposes. Using thisprocedure, we can produce near optimal interconnect sharing schemes in a few seconds for most practical sizepipelined designs. This efficient approach will enable designers to explore a larger portion of the design spaceand trade off various design parameters effectively.

Nohbyung  Park

Fadi J. Kurdahi

Register-Transfer Synthesis of Pipelined Data Paths

In this paper, we describe algorithms based on Simulated Annealing for selecting a subset of flip-flops to be
connected into a scan path. The objective for selection is to maximize the coverage of faults that are aborted by
a sequential fault simulator. We pose the problem as a combinatorial optimization, and present a heuristic algorithm
based on Simulated Annealing. The SCOAP testability measure is employed to assess the selection of flip-flops
during the course of optimization. Our algorithms form a part of an integrated design package, TOPS, which has
been designed as an enhancement to the OASIS standard-cell design automation system available from MCNC.
We discuss the TOPS package and its performance on a number of ISCAS'89 benchmarks. We also present a
comparative evaluation of the benchmark results.

C. P. Ravikumar

H. Rasheed

TOPS: A Target-Oriented Partial Scan Design
Package Based on Simulated Annealing

Channel routing problem is an important, time consuming and difficult problem in VLSI layout design. In thispaper, we consider the two-terminal channel routing problem in a new routing model, called knock-knee diagonalmodel, where the grid consists of right and left tracks displayed at +45&#176; and &#8211;45&#176;. An optimum algorithm ispresented, which obtains d + 1 as an upper bound to the channel width, where d is the channel density.

Xiaoyu  Song

An Optimum Channel Routing Algorithm in theKnock-knee Diagonal Model

A data path consists of memory elements (i.e. registers), data operators (i.e. ALUs) and interconnection units(i.e. buses) to control the data transfers in the digital system. Many approaches to memory synthesis have beenproposed in the literature. However, only single port memory is considered for register allocation and no efficientsynthesis approach for multiport memory synthesis. In this paper, an efficient method, Partitioned Dependence Matrix (PDM), is presented for memory synthesis which deals not only with single port memory synthesis butalso multiport memory synthesis according to the design constraints. With suitable modifications, the proposedtechnique can also be applied to multiport memory synthesis in which the maximum number of read ports isdifferent from the maximum number of write ports. Therefore, the entire design space is explored and has thecapability to handle early architectural design exploration so that the quality of designs produced by an automaticsynthesis tool is more adequate for production use in comparison to manual design. Illustrations of applying thismethod to different synthesis examples are presented. Results and improvements over previous techniques aredemonstrated. A key element in our approach is the successful adoption of techniques originally developed forproblems in test generation to the field of memory synthesis.

Chien-In Henry Chen

Using PDM on Multiport Memory Allocationin Data Path

The testability distribution of a VLSI circuit is modeled as a series of step functions over the interval [0, 1]. Themodel generalizes previous related work on testability. Unlike previous work, however, we include estimates oftestability by random vectors. Quadratic programming methods are used to estimate the parameters of thetestability distribution from fault coverage data (random and deterministic) on a sample of faults. The estimatedtestability is then used to predict the random and deterministic fault coverage distributions without the need toemploy test generation or fault simulations. The prediction of fault coverage distribution can answer importantquestions about the &#8220;goodness&#8221; of a design from a testing point of view. Experimental results are given on thelarge ISCAS-85 and ISCAS-89 circuits.

H.  Farhat

S.  From

A Quadratic Programming Approach to Estimatingthe Testability and Random or DeterministicCoverage of a VLSl Circuit

Two algorithms to partition hole-free rectilinear polygons are developed. One has complexity &#8764; O(kn) and theother O(n log k) where n is the number of vertices in the polygon and k is the smaller of the number of verticaland horizontal inversions of the polygon, k is a measure of the simplicity of a polygon. Since k is small for mostpractical polygons, our algorithms are fast in practice. Experimental results comparing our algorithms with thatof Imai and Asano [1] are also presented.

San-Yuan  Wu

Sartaj  Sahni

Fast Algorithms to Partition Simple RectilinearPolygons

This paper presents techniques for designing arbitrary combinational circuits so that any single stuck-at fault will
result in either single bit error or unidirectional multibit error at the output. If the outputs are encoded using
Berger code or m-out-of-n code, then the proposed technique will enable on-line detection of faults in the circuit.
An algorithm for indicating whether a certain fault at an input will create bidirectional error at the output is
presented. An input encoding algorithm and an output encoding algorithm that ensure that every fault will either
produce single bit error or unidirectional multibit error at the output are proposed. If there are no input fault
which produces bidirectional error, no internal stuck-at fault will result in such an error irrespective of the way
the circuit is implemented. Thus, only single bit or unidirectional multibit error will result in the presence of a
fault in the circuit. The proposed techniques have been applied to MCNC benchmark circuits and the overhead
is estimated.

Fadi Busaba

Parag K. Lala

Techniques for Self-Checking Combinational Logic
Synthesis

In this paper, we describe a highly efficient automatic test pattern generator for stuck-open (SOP) faults, calledSOPRANO, in CMOS combinational circuits. The key idea of SOPRANO is to convert a CMOS circuit into anequivalent gate level circuit and SOP faults into the equivalent stuck-at faults. Then SOPRANO derives testpatterns for SOP faults using a gate level test pattern generator. Several techniques to reduce the test set sizeare introduced in SOPRANO. Experimental results performed on eight benchmark circuits show that SOPRANOachieves high SOP fault coverage and short processing time.

Hyung K. Lee

Dong S. Ha

An Efficient Automatic Test Pattern Generator forStuck-Open Faults in CMOS Combinational Circuits

New, efficient algorithms for the automated synthesis of buses in data path design are presented. Modifications
to the technique of Generalized Clique Partitioning (GCP) are discussed which lead to better designs and reduced
computation time in large synthesis problems. The new approach, Weighted Cluster Partitioning (WCP), eliminates
the need for backtracking. The algorithm guides the process of bus formation by assigning a higher weight to
those interconnection units that should be combined first. The operation of the WCP algorithm is clearly demonstrated
using a detailed example.A modified priority ordering in the selection of the candidate pair is also discussed which can improve the
performance of GCP and WCP. We demonstrate that GCP II performs better than GCP, while WCP II consistently
produces the best results of all these algorithms on a set of large synthesis examples.

Gerald Sobelman

Cluster Partitioning Techniques for Data Path
Synthesis

Based on the demand-driven approach, distributed and parallel simulation algorithms are proposed. Demand-driven
simulation ties to minimize the number of component evaluations by restricting to only those component
computations required for the watched output requests. For a specific output value request, the input line values
that are required are requested to the respective component. The process continues until known signal values
are needed (system input signal values). We present a distributed demand-driven algorithm with infinite memory
requirement (but still the memory required at each process is no greater than the sequential demand-driven
simulation), and a parallel demand-driven simulation with finite memory requirement. In our algorithms, each
component is assigned a logical process.The algorithms have been implemented on the Sequent Balance 8000 Multi-processor machine. Several sample
circuits were simulated. The algorithms were compared with the distributed discrete-event simulation. Our distributed
algorithm performed many times faster than the discrete-event simulation for cases when few results
were needed. Parallel algorithm performed 2 to 4 times faster than the distributed discrete-event simulation.

K. Subramanian

M. Zargham

Distributed and Parallel Demand Driven Logic
Simulation Algorithms

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VLSI Design

Table of Contents

Table of Contents: 1994

Modular Scheme for Designing Special Purpose Associative Memories and Beyond

Special Issue on Digital Hardware Testing

An Improved Data Flow Architecture for Logic Simulation Acceleration

SEGMA: A Simulated Evolution Gate-Matrix Layout Algorithm

Block-Level Logic Extraction from CMOS VLSI Layouts

Register-Transfer Synthesis of Pipelined Data Paths

TOPS: A Target-Oriented Partial Scan Design Package Based on Simulated Annealing

An Optimum Channel Routing Algorithm in the Knock-knee Diagonal Model

Using PDM on Multiport Memory Allocation in Data Path

A Quadratic Programming Approach to Estimating the Testability and Random or Deterministic Coverage of a VLSl Circuit

Fast Algorithms to Partition Simple Rectilinear Polygons

Techniques for Self-Checking Combinational Logic Synthesis

An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits

Cluster Partitioning Techniques for Data Path Synthesis

Distributed and Parallel Demand Driven Logic Simulation Algorithms