A novel approach, called PGEN, is proposed to generate test patterns for resettable or nonresettable synchronous sequential circuits. PGEN contains two major routines, Sequential PODEM (S-PODEM) and a differential fault simulator. Given a fault, S-PODEM uses the concept of multiple time compression supported by a pulsating model, and generates a test vector in a single (yet compressed) time frame. Logic simulation (included in S-PODEM) is invoked to expand the single test vector into a test sequence. The single test vector generation methodology and logic simulation are well coordinated and significantly facilitate sequential circuit test generation. A modified version of differential fault simulation is also implemented and included in PGEN to cover other faults detected by the expanded test sequence. Experiments using computer simulation have been conducted, and results are quite satisfactory.

Wen-Ben Jone

Nigam Shah

Anita Gleason

Sunil R. Das

PGEN: A Novel Approach to Sequential Circuit Test Generation

Guest Editorial

This paper presents a hardware implementation of design rule checker using a specialized Content Addressable Memory(CAM) for the Manhattan geometric designs. Two dimensional relationships between rectangular objects in a design are checked with one dimensional design rules. The input data is processed by the pixel pre-processor in such a way that direct comparison between the input data and the stored rules in the CAM is possible. The comparison by the CAM reduces the number of memory references and logic operations of pattern matching and the simple architecture of the system enables a low cost implementation.

Seokjin  Kim

Ramalingam  Sridhar

Hardware Design Rule Checker Using a CAM Architecture

This paper investigates the possibility of using Field-Programmable Gate Arrays (Fpgas) as reconfigurable co-processors for workstations to produce moderate speedups for most tasks in the design process, resulting in a worthwhile overall design process speedup at low cost and allowing algorithm upgrades with no hardware modification. The use of Fpgas as hardware accelerators is reviewed and then achievable speedups are predicted for logic simulation and VLSI design rule checking tasks for various Fpga co-processor arrangements.

Neil J. Howard

Andrew M. Tyrrell

Nigel M. Allinson

The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks

In order to reduce cost and to achieve high speed a new hardware accelerator for fault simulation has been designed. The architecture of the new accelerator is based on a reconfigurabl mesh type processing element (PE) array. Circuit elements at the same topological level are simulated concurrently, as in a pipelined process. A new parallel simulation algorithm expands all of the gates to two input gates in order to limit the number of faults to two at each gate, so that the faults can be distributed uniformly throughout the PE array. The PE array reconfiguration operation provides a simulation speed advantage by maximizing the use of each PE cell.This new approach provides for a high performance, cost effective, gain over software simulation. Simulation results show that the hardware accelerator is orders of magnitude faster than the software simulation program.

Sungho  Kang

Youngmin  Hur

Stephen A. Szygenda

A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture

A hardware architecture is proposed which allows direct mapping of design simulation topology onto an acceleration platform. In order to clarify architectural principles, the simulation is confined to functional verification of unit delay, binary valued gate level logic designs. Under this approach, a rank ordered design description is executed on a massively parallel processor grid which implements an efficient and direct model of the design, similar to prototyping. Architectural innovation reduces logic complexity and execution time ofboolean evaluation and fanout switching circuits, while large scale parallelism is integrated at die level to reduce cost and communication delays. The results of this research form the basis for a multiple order of magnitude improvement in reported state-of-the-art cost-performance merit for hardware gate level simulation accelerators.

E. Scott Fehr

Granville E. Ott

An Integrated Hardware Array for Very High Speed Logic Simulation

A recent paper by Bailey [1] contains a theorem stating that the idealized execution times of unit-delay, synchronous and conservative asynchronous simulations are equal under the conditions that unlimited number of processors are available and the evaluation time of each logic element is equal. Further it is shown that the above conditions result in a lower bound on the execution times of both synchronous and conservative asynchronous simulations. Bailey's above important conclusions are derived under a strict assumption that the inputs to
a circuit remain fixed during the entire simulation. We remove this limitation and, by extending the analyses to multi-input, multi-output circuits with an arbitrary number of input events, show that the conservative asynchronous simulation extracts more parallelism and executes faster than synchronous simulation in general. Our conclusions are supported by a comparison of the idealized execution times of synchronous and conservative asynchronous algorithms on ISCAS combinational and sequential benchmark circuits.

Ausif Mahmood

William I. Baker

An Evaluation of Parallel Synchronous and Conservative Asynchronous Logic-Level Simulations

Ausif  Mahmood

Hardware Accelerators for VLSI Design

This paper describes the design of an ASIC chip for thinning of graylevel images. The chip implements a Min-Max skeletonization algorithm and is based on a pipeline architecture where each stage of the pipeline performs masking operations on the graylevel images. The chip operates in real time at a frequency of 8 MHz and utilizes about 321 mils &#215; 410 mils of silicon area.

B.  Majumdar

V. V. Ramakrishna

P. S. Dey

A. K. Majumdar

Design of an ASIC Chip for Skeletonization of Graylevel Digital Images

This paper presents a router for routing multi-terminal nets in field-programmable gate arrays (FPGAs). The router does not require pre-assignment of routing channels, a phase that is normally accomplished during global routing. This direct routing approach greatly enhances the probability of routing (routability). The multi-terminal routing greatly reduces the total wire length as it approximates a Steiner tree. The total number of segments required to route the circuits is usually less as compared to other routing approaches. The router has generated excellent routing results for some industrial circuits. The memory requirements for this router are very low. The time needed for the routing is linear with respect to the size of the circuit.

Dinesh  Bhatia

Amit  Chowdhary

A Multi-Terminal Net Router for Field-Programmable Gate Arrays

A linear time algorithm for routing over the cells is presented. The algorithm tries to reduce
maximum channel density by routing some connections over the cells. The algorithm first
defines a new scheme for channel representation and formulates the problem based on an
intersection graph derived from the new scheme. Then, a feasible independent set of the
intersection graph is found for routing some subnets over the cells. The algorithm is implemented
and evaluated with several well known benchmarks. In comparison with previous
research, our results are satisfactory, and the algorithm takes substantially less CPU time
than those of previous works. For Deutsch's difficult example, the previous algorithms take
about 29.25 seconds on an average but our new algorithm needs only 5.6 seconds.

Kuo-En Chang

Sei-Wang Chen

An Efficient and Fast Algorithm for Routing
Over the Cells

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