Farid N. Najm

Gary  Yeap

Guest Editorial

Jack  Jean

Sanjaya  Kumar

This paper presents the design methodology used in PSS1, a high level synthesis system
designed for computation dominated applications. It includes a behavior synthesizer and an
area optimizer. Based on a pre-defined architecture, the behavior synthesizer translates a
description into a number of designs with different delays and hardware costs. Based on a
two-level layout model, the area optimizer fine-tunes the physical design using the information
feedback from the layout tools. All the tools are linked by an X-window interface in
which users can traverse among different tools and interactively change the design parameters.
The output is linked to Lager system [7], a silicon assembler. The layout model allows
a designer to interactively merge/split modules, change the shape of modules, and define the
pin positions of modules. Experiments show that a considerable area improvement has been
achieved using this methodology.

Fur-Shing Tsai

Yu-Chin Hsu

Layout Modeling and Design Space Exploration in Pss1 System

Mathematically the most difficult partitioning problem&#8211;packaging&#8211;is being considered.Its purpose is to minimize a number of partitions and to satisfy the constraints onthe number of constituent elements and external nets. To solve the problem, the OptimalCircuit Reduction Method, suggested by R. Bazylevych is being used. The optimalreduction tree to reflect the hierarchical entrance of smaller clusters into bigger ones isbeing built for the first step. At the second step we select one or more tree vertices whichbetter meet the given constraints and are the first partitions generated from. Aftercreating every new partition we eliminate its elements from the circuit and repeat theprocedure to complete all partitions. During the last stage optimization strategies toexchange some elements between the partitions are being used. Better or equivalentresults among known tests confirm the effectiveness of this method.

R. P. Bazylevych

R. A. Melnyk

O. G. Rybak

Circuit Partitioning for FPGAs by the Optimal Circuit Reduction Method

We investigate conservative parallel discrete event simulations for logical circuits on
shared-memory multiprocessors. For a first estimation of the possible speedup, we
extend the critical path analysis technique by partitioning strategies. To incorporate
overhead due to the management of data structures, we use a simulation on an ideal
parallel machine (PRAM). This simulation can be directly executed on the SB-PRAM
prototype, yielding both an implementation and a basis for data structure optimizations.
One of the major tools to achieve these optimizations is the SB-PRAM's
hardware support for parallel prefix operations. Our reimplementation of the PTHOR
program on the SB-PRAM yields substantially higher speedups than before.

Jörg Keller

Thomas Rauber

Bernd Rederlechner

Scalability Analysis for Conservative Simulation
of Logical Circuits

The phenomenon of resonant tunneling is simulated and analyzed in the quantum hydrodynamic (QHD) modelfor semiconductor devices. Simulations of a parabolic well resonant tunneling diode at 77 K are presented whichshow multiple regions of negative differential resistance (NDR) in the current-voltage curve. These are the firstsimulations of the QHD equations to show multiple regions of NDR.Resonant tunneling (and NDR) depend on the quantum interference of electron wavefunctions and thereforeon the phases of the wavefunctions. An analysis of the QHD equations using a moment expansion of theWigner-Boltzmann equation indicates how phase information is retained in the hydrodynamic equations.

Carl L. Gardner

Resonant Tunneling in the QuantumHydrodynamic Model

An empirical algorithm applied to logic level power analysis in deep submicron VLSI designs is introduced in the paper. The method explores a static analysis strategy using unit functions to represent signal transitions. It can be extended to the use of a Register Transfer Level (RTL) power analysis after RTL codes are translated to Boolean equations. A new method for representing state-dependent power models is also introduced in the paper to reduce the complexity of power modeling and to improve the performance of power analysis. The modeling method supports not only the empirical power analysis, but also general simulation-based power analysis methods.

May  Huang

Raymond  Kwok

Shu-park  Chan

An Empirical Algorithm for Power Analysis in Deep Submicron Electronic Designs

Fluctuation effects are becoming important in advanced VLSI devices because of theirincreasing impact on circuit performance and chip yields. Accurate modelling of theseeffects generally requires full 3D simulation, which is used here to analyse four of theprimary such effects. Polysilicon line edge roughness causes excess device leakage, whichcan be reduced at the cost of decreased performance. Phase-shift mask defects canreduce current drive and increase capacitance. Random dopant fluctuation, whichcauses variation in threshold voltage, is evaluated for three technology generations andit is shown that proper tip scaling can reduce these variations. Finally, a study of alphaparticle strikes evaluates the effectiveness of SOI in improving soft error reliability.

Thomas D. Linton

Shaofeng  Yu

Reaz  Shaheed

3D Modelling of Fluctuation Effects in HighlyScaled VLSI Devices

Azzedine  Boukerche

We present a new approach to the power modeling of functional modules, referred to as
the backward propagated capacitance model, for estimating the power consumption of
VLSI systems that are described at the register transfer level (RTL). To construct the
proposed model, we investigate the effect of the module's internal capacitance on power
consumption at the gate level. Then, we store the effect in a library in terms of the
equivalent input capacitance of the module. The equivalent input capacitance is used to
compute the module's power without the lower level elaboration during the power
analysis of the RTL system. In the experiment using benchmark functional modules, the
proposed model showed the absolute modeling error of 1.39% on average. For the
benchmark RTL systems, the proposed model exhibited the absolute error of 3.04% in
power estimation on average. If signal characteristics deviate from the modeling
condition, the modeling error may increase. Experimental results show that the
modeling accuracy can be improved greatly by using a simple compensation method.

Jung Yun Choi

Young Hwan Kim

Kyoung-Rok Cho

Backward Propagated Capacitance Model for Register Transfer Level Power Estimation

Two algorithms to partition hole-free rectilinear polygons are developed. One has complexity &#8764; O(kn) and theother O(n log k) where n is the number of vertices in the polygon and k is the smaller of the number of verticaland horizontal inversions of the polygon, k is a measure of the simplicity of a polygon. Since k is small for mostpractical polygons, our algorithms are fast in practice. Experimental results comparing our algorithms with thatof Imai and Asano [1] are also presented.

San-Yuan  Wu

Sartaj  Sahni

Fast Algorithms to Partition Simple RectilinearPolygons

Most datapath synthesis approaches use a simple area model to evaluate design area quality.However, using such a simplified model could mislead synthesis tasks into generating inferiordesigns. This paper presents an extensive experimental study to validate the correlationbetween the tradition area model, our proposed area model, and the actual layouts. Theresults show that traditional area quality measures are not good indicators for optimization indatapath synthesis. Moreover, this paper also shows that to provide accurate indications fordesign tradeoffs in high-level synthesis, the fidelity of the estimates is more important thanthe accuracy.

Allen C.-H. Wu

Datapath Optimization Using Layout Information: An Empirical Study

We consider the problem of selecting the proper implementation of each circuit module
from a cell library to minimize the propagation delay along every path from any primary input to any primary output subject to an upper bound on the total area of the circuit.
Different module implementations may have different areas and delays on the paths. Wc
show that the latter problem is NP-hard even for directed acyclic graphs with two
implementations per module and no restrictions on the overall area of the circuit. Wc
present a novel retiming based heuristic for determining the minimum clock period on
sequential circuits. Although our heuristics may handle a bound on the total area of the
circuit, emphasis is given on the timing issue.

Dimitrios Karayiannis

Spyros Tragoudas

Timing-Driven Circuit Implementation

The nonequilibrium total dielectric function lends itself to a simple and general method forcalculating the inelastic collision term in the electron Boltzmann equation for scattering froma coupled mode system. Useful applications include scattering from plasmon-polar phononhybrid modes in modulation doped semiconductor structures. This paper presents numericalmethods for including inelastic scattering at momentum-dependent hybrid phonon frequenciesin the low-field Boltzmann equation for two-dimensional electrons coupled to bulk phonons.Results for electron mobility in GaAs show that the influence of mode coupling anddynamical screening on electron scattering from polar optical phonons is stronger for twodimensional electrons than was previously found for the three dimensional case.

B. A. Sanborn

Total Dielectric Function Approachto the Electron Boltzmann Equation for Scatteringfrom a Two-Dimensional Coupled Mode System

Sunil R. Das

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