VLSI Design

Module Selection in Microarchitectural Synthesis for Multiple Critical Constraint Satisfaction

Mixed-RKDG Finite Element Methods for the 2-D Hydrodynamic Model for Semiconductor Device Simulation

Memory Chips with Adjustable Configurations

Partitioning Techniques for Built-In Self-Test Design

The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks

Quantum Contributions and Violations of the Classical Law of Mass Action

Geometric Design Rule Check of VLSI Layouts in Distributed Computing Environment

Computation Reordering: A Novel Transformation for Low Power DSP Synthesis

The Response of the Hydrodynamic Model to Heat Conduction, Mobility, and Relaxation Expressions

Non-linear Hybrid Cellular Automata as Pseudorandom Pattern Generators for VLSI Systems

A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture

RT Component Sets for High-Level Design Applications

Langevin Forces and Generalized Transfer Fields for Noise Modelling in Deep Submicron Devices

Channel Density Minimization by Pin Permutation

A Parallel Residue-to-binary Converter for the Moduli Set

VLSI Design

Table of Contents

Table of Contents

Module Selection in Microarchitectural Synthesis for Multiple Critical Constraint Satisfaction

Mixed-RKDG Finite Element Methods for the 2-D Hydrodynamic Model for Semiconductor Device Simulation

Memory Chips with Adjustable Configurations

Partitioning Techniques for Built-In Self-Test Design

The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks

Quantum Contributions and Violations of the Classical Law of Mass Action

Geometric Design Rule Check of VLSI Layouts in Distributed Computing Environment

Computation Reordering: A Novel Transformation for Low Power DSP Synthesis

The Response of the Hydrodynamic Model to Heat Conduction, Mobility, and Relaxation Expressions

Non-linear Hybrid Cellular Automata as Pseudorandom Pattern Generators for VLSI Systems

A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture

RT Component Sets for High-Level Design Applications

Langevin Forces and Generalized Transfer Fields for Noise Modelling in Deep Submicron Devices

Channel Density Minimization by Pin Permutation

A Parallel Residue-to-binary Converter for the Moduli Set