The System Level Applications of Adaptive Computing (SLAAC) project is defining anopen, distributed, scalable, adaptive computing systems architecture based on a highspeednetwork cluster of heterogeneous, FPGA-accelerated nodes. Two reference implementationsof this architecture are being created. The Research Reference Platform(RRP) is a MyrinetTM cluster of PCs with PCI-based FPGA accelerators (SLAAC-1).The Deployable Reference Platform (DRP) is a Myrinet cluster of PowerPCTM nodeswith VME-based FPGA accelerators (SLAAC-2) and a commercial 6U-VME quad-PowerPC board (CSPI M2641S) serving as the carrier. A key strategy proposed forsuccessful ACS technology insertions is source-code compatibility between the RRP andDRP platforms. This paper focuses on the development of the SLAAC-1 and SLAAC-2accelerators and how the network-centric SLAAC system-level architecture has shapedtheir designs. A preliminary mapping of a Synthetic Aperture Radar/Automatic TargetRecognition (SAR/ATR) algorithm to SLAAC-2 is also discussed.

Brian  Schott

Stephen P. Crago

Robert H. Parker

Chen H. Chen

Lauretta C. Carter

Joseph P. Czarnaski

Matthew  French

Ivan  Hom

Tam  Tho

Terri  Valenti

Reconfigurable Architectures for System LevelApplications of Adaptive Computing

This paper presents a state assignment algorithm with the objective of lower energyalong with area comparable to the area-targeting state assignments such as JEDI. Theunderlying framework is MUSTANG&#39;s complete weighted graph with weights representingstate affinity. The weight computation phase estimates the computation energyof potential common cubes using steady state probabilities for transitions. The weightcomputation phase also identifies a large set of potential state cliques, which are incorporatedinto a recursive bipartitioning based state assignment procedure. Reuse ofcliques identified by the weight computation phase results in a faster and efficient stateassignment. The energy targeting weights result in &#8776;9&#37; lower area and 18&#37; lowerpower than area targeting weights in JEDI over 29 MCNC Logic Synthesis &#145;93 benchmarks.The clique based state assignment performs almost as well as the annealingbased state assignment in JEDI, and takes only about half as much time.

Akhilesh  Tyagi

Integrated Area-power Optimal State Assignment

Higher levels of integration have led to a generation of integrated circuits for which
power dissipation and reliability are major design concerns. In CMOS circuits, both of
these problems are directly related to the extent of circuit switching activity. The average
number of transitions per second at a circuit node is a measure of switching activity that
has been called the transition density. This paper presents a statistical simulation
technique to estimate individual node transition densities in combinational logic
circuits. The strength of this approach is that the desired accuracy and confidence can be
specified up-front by the user. Another key feature is the classification of nodes into two
categories: regular- and low-density nodes. Regular-density nodes are certified with
user-specified percentage error and confidence levels. Low-density nodes are certified
with an absolute error, with the same confidence. This speeds convergence while
sacrificing percentage accuracy only on nodes which contribute little to power
dissipation and have few reliability problems.

Farid N. Najm

Michael G. Xakellis

Statistical Estimation of the ,Switching Activity in VLSI Circuits

The paper identifies the inefficiencies of the critical processes in concurrent fault simulation and proposes methods to remove such inefficiencies in a systematic manner. Also, proposed are dynamic memory usage reduction strategies for concurrent fault simulators. Through extensive step-by-step experimentation, we verified the effectiveness of the proposed methods for performance improvement and identified best memory management strategy for dynamic memory usage reduction. A simulator, HySim, based on the proposed methods is implemented and shown to outperform the existing fault simulators and achieve dramatic memory usage reduction. The HySim maintains fault lists which are subsets of that of a conventional concurrent fault simulator, which yields shorter fault list processing time and reduced dynamic memory usage. It also employs Release-and-Reconstruct method for fault list construction, where any fault list identified to be useless is released immediately. The experimental results show that Release-and-Reconstruct method is very effective in dynamic memory usage reduction.

Kyuchull Kim

Kewal K. Saluja

HYSIM: Hybrid Fault Simulation for Synchronous Sequential Circuits

This paper describes a Prolog based Block Extraction System (ProBES) which converts a transistor level descriptionof a CMOS circuit into a logic block level description. The operation of ProBES is conceptually similar to thatof a circuit extractor. However, whereas a circuit extractor is used to identify circuit primitives such as transistors,resistors and capacitors from the geometrical information in a mask level layout description, ProBES can be usedto identify predefined gates and logic blocks in a CMOS transistor network. ProBES operates according to thecircuit hierarchy. Basic gates such as inverters, transmission-gates, nands, nors, etc. are identified first. Logicblocks composed of these gates are then identified. More complex blocks which contain blocks already identifiedare recognized next and so on. ProBES is meant to be used as an aid in the verification of logic design. It canprovide a connectivity check for a circuit.

Inderpreet  Bhasin

Joseph G. Tront

Block-Level Logic Extraction from CMOS VLSILayouts

Delay, power, skew, area and sensitivity are the most important concerns in current clock-tree design. We present in this paper an algorithm for simultaneously optimizing the above objectives by sizing wires and buffers in clock trees. Our algorithm, based on Lagrangian relaxation method, can optimally minimize delay, power and area simultaneously with very low skew and sensitivity. With linear storage overall and linear runtime per iteration, our algorithm is extremely economical, fast and accurate; for example, our algorithm can solve a 6201-wire-segment clock-tree problem using about 1-minute runtime and 1.3-MB memory and still achieve pico-second precision on an IBM RS/6000 workstation.

Yu-Min  Lee

Charlie Chung-Ping Chen

Yao-Wen  Chang

D. F. Wong

Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation

To find a minimal expression of a boolean function includes a step to select the minimum cost cover from a set ofimplicants. Since the selection process is an NP-complete problem, to find an optimal solution is impractical forlarge input data size. Neural network approach is used to solve this problem. We first formalize the problem, andthen define an &#8220;energy function&#8221; and map it to a modified Hopfield network, which will automatically search forthe minima. Simulation of simple examples shows the proposed neural network can obtain good solutions most ofthe time.

Pong P. Chu

Applying Neural Networks to Findthe Minimum Cost Coverageof a Boolean Function

In this paper new methods for the transformation of a given combinational circuit into
a self-dual circuit based on the notion of a self-dual complement are investigated. The
large variety of self-dual complements can be utilized to optimize the transformed self-dual
circuit. Self-dual duplication and self-dual parity prediction are considered in
detail. As a method for the reduction of self-dual outputs, output space compaction of
self-dual outputs is considered. For the first time we also describe in this paper how a
self-dual circuit can be modified into a self-dual fault-secure circuit.

A. Dmitriev

V. Saposhnikov

Vl. Saposhnikov

M. Goessel

Vl. Moshanin

A. Morosov

New Self-dual Circuits for Error Detection and Testing

For a building block placement, the routing space can be further partitioned into channels and switchboxes. In general, the definition of switchboxes releases the cyclic channel precedence constraints and further yields a safe routing ordering process. However, switchbox routing is more difficult than channel routing. In this paper, an O(NlogN) region definition and ordering assignment (RDAOA) algorithm is proposed to minimize the number of switchboxes for the routing phase, where N is the number of vertices in a channel precedence graph. Several examples have been tested on the proposed algorithm, and the experimental results are listed and compared.

Jin-Tai  Yan

Pei-Yung  Hsiao

An O(NlogN) Algorithm for Region Definition Using Channels/Switchboxes and Ordering Assignment

Sunil R. Das

Guest Editorial

We present a new approach to the problem of register-transfer level design optimization of pipelined data paths.The output of high level synthesis procedures, such as Sehwa, consists of a schedule of operations into time steps,and a fixed set of hardware operators. In order to obtain a register-transfer level design, we must assign operationsto specific operators, values to registers, and finish the interconnections. We first perform module assignmentwith the goal of minimizing the interconnect requirements between RT-level components as a preprocessingprocedure to the RT-level design. This will result in a smaller netlist which makes the design more compact andthe design process more efficient. In addition to reducing the total number of interconnects, this approach willalso reduce the total number of multiplexors in the design by eliminating unnecessary multiplexing at the inputsof shared modules. The interconnect sharing task is modeled as a constrained clique partitioning problem. Wedeveloped a fast and efficient polynomial time heuristic procedure to solve this problem. This procedure is 30&#8211;50 times faster than other existing heuristics while still producing better results for our purposes. Using thisprocedure, we can produce near optimal interconnect sharing schemes in a few seconds for most practical sizepipelined designs. This efficient approach will enable designers to explore a larger portion of the design spaceand trade off various design parameters effectively.

Nohbyung  Park

Fadi J. Kurdahi

Register-Transfer Synthesis of Pipelined Data Paths

Important layout properties of electronic circuits include space requirements and
interconnection lengths. In the process of designing these circuits, a reliable pre-layout
interconnection length estimation is essential for improving placement and routing
techniques. Donath found an upper bound for the average interconnection length that
follows the trends of experimentally observed average lengths. Yet, this upper bound
deviates from the experimental value by a factor <mml:math id="E1" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>δ</mml:mi><mml:mtext> </mml:mtext><mml:mo>≈</mml:mo><mml:mtext> </mml:mtext><mml:mn>2</mml:mn></mml:mrow></mml:math>, which is not sufficiently accurate
for some applications. We show that we obtain a significantly more accurate estimate by
taking into account the inherent features of the optimal placement process.

Dirk Stroobandt

Jan  Van Campenhout

Accurate Interconnection Length Estimations for Predictions Early in the Design Cycle

The importance of 2-dimensional (2D) features of carriers in Si MOSFETs on the deviceperformance is re-examined experimentally and theoretically from the viewpoint of low-fieldmobility, velocity in high tangential fields and the inversion-layer capacitance. It isconfirmed that low-field mobility and inversion-layer capacitance can be understoodwell in terms of the 2D subbands and the 2D carrier transport. In order to obtain fully-quantitativeunderstanding of low-field mobility, however, it is still necessary to moreaccurately determine the amount of the scattering parameters in the inversion layer. Onthe other hand, saturation velocity is considered to be less influenced by the 2Dquantization, while it is found experimentally that saturation velocity is slightlydependent on surface carrier concentration.According to the knowledge of 2-dimensional carrier transport in Si inversion layer,an effective way to have higher current drive is to increase the occupancy of the 2-foldvalleys, which have lower conductivity mass, on a (100) surface. From this viewpoint,two device structures, strained Si MOSFETs and SOI MOSFETs with ultra-thin SOIfilms, are introduced and the behavior of low-field mobility is analyzed through thecalculations of the subband structures and phonon-limited mobility.

Shin-Ichi  Takagi

Two-dimensional Carrier Transport in Si MOSFETs

An efficient solution to the generalized detailed routing problem in segmented channels for
row-based FPGAs is presented. A generalized detailed routing allows routing of each connection
using an arbitrary number of tracks, i.e., doglegs are allowed. This approach is
different from the normally followed method where each connection is routed on a single
straight track. We present a router that performs generalized segmented channel routing
using a greedy approach to route channels. The router also renders itself to limited tolerance
against faults in the routing architecture.

Dinesh Bhatia

V. Shankar

Greedy Segmented Channel Router

Most algorithms for reconfigurable meshes (R-meshes) are based on the divide-and-conquer(DAC) strategy. Although the strategy per se does not require the subproblemsto be equal in size, existing DAC algorithms for R-meshes do divide the problemapproximately evenly. This paper demonstrates that dividing a problem evenly is notnecessarily a good way to decompose a problem. There are occasions on which anirregular decomposition scheme may be preferable. We take this approach and obtain anew sorting algorithm. Our sorting algorithm has several strengths: it is simple, scalable,and as broadcast-efficient as the best known result.

Ten H. Lai

Ming-Jye  Sheng

Sorting on Reconfigurable Meshes:An Irregular Decomposition Approach

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VLSI Design