Power consumption in a synchronous FSM (Finite-State Machine) can be reduced by
partitioning it into a number of coupled sub-FSMs where only the part that is involved
in a state transition is clocked. Automatic synthesis of a partitioned FSM includes a
partitioning algorithm and sub-FSM synthesis to an implementation architecture. In
this paper, we first introduce an implementation architecture for partitioned FSMs that
uses gated-clock technique for disabling idle parts of the circuits and asynchronous
controllers for communication between the sub-FSMs. We then describe a new transformation
procedure for the sub-FSM. The FSM synthesis flow has been automated in a
prototype tool that accepts an FSM specification. The tool generates synthesizable RT-level
VHDL code with identical cycle-to-cycle input/output behavior in accordance
with the specification. An average power reduction of 45% has been obtained for a set
standard FSM benchmarks.

Bengt Oelmann

Kalle Tammemäe

Margus Kruus

Mattias O'Nils

Automatic FSM Synthesis for Low-power Mixed Synchronous/Asynchronous Implementation

A finite element method based on the least-squares scheme is developed for hydrodynamic
simulation of two-dimensional short-channel semiconductor devices. Although
this general-purpose finite element method has been shown in fluid dynamics to be more
universal to flow problems than other finite element approaches and has been applied in
recent years to a wide range of problems in fluid dynamics, it is still unfamiliar to the
semiconductor device community. Application of the developed hydrodynamic least
squares finite element method (LSFEM) to simulation of a 2D MESFET with a deep-submicron
gate has demonstrated its robustness and effectiveness for the hydrodynamic
device simulation.

Min Shen

Ming-C. Cheng

J. J. Liou

A Generalized Finite Element
Method for Hydrodynamic
Modeling of Short-channel Devices

Memory system usually consumes a significant amount of energy in many battery-operateddevices. In this paper, we provide a quantitative comparison and evaluation ofthe interaction of two hardware cache optimization mechanisms and three widely usedcompiler optimization techniques used to reduce the memory system energy. Ourpresentation is in two parts. First, we focus on a set of memory-intensive benchmarkcodes and investigate their memory system energy behavior due to data accesses underhardware and compiler optimizations. Then, using four motion estimation codes, welook at the influence of compiler optimizations on the memory system energyconsidering the overall impact of instruction and data accesses.

G.  Esakkimuthu

H. S. Kim

M.  Kandemir

N.  Vijaykrishnan

M. J. Irwin

Investigating Memory System Energy Behavior Using Software and Hardware Optimizations

We discuss a full three-dimensional model of an ultra-small MOSFET, in which the
transport is treated by a coupled EMC and molecular dynamics (MD) procedure to
treat the Coulomb interaction in real space. The inclusion of the proper Coulomb
interaction affects both the energy and momentum relaxation processes, but also has a
dramatic effect on the characteristic curves of the device. We find that the short-range
e–e and e–i terms, combined with discrete impurity effects, is also needed for accurate
measurement of the device threshold voltage.

W. J. Gross

D. Vasileska

D. K. Ferry

Ultra-small MOSFETs: The Importance of the Full
Coulomb Interaction on Device Characteristics

Power efficient design of real-time embedded systems based on programmable processorsbecomes more important as system functionality is increasingly realized throughsoftware. We address a power optimization method for real-time embedded applicationson a variable speed processor. The method combines off-line and on-line components.The off-line component determines the lowest possible maximum processor speed whileguaranteeing deadlines of all tasks. The on-line component dynamically varies the processorspeed or bring a processor into a power-down mode to exploit execution timevariations and idle intervals. Experimental results show that the proposed methodobtains a significant power reduction across several kinds of applications.

Youngsoo  Shin

Kiyoung  Choi

Takayasu  Sakurai

Power-conscious Scheduling for Real-time Embedded Systems Design

We present a framework for combining Voltage Scaling (VS) and Gate Sizing (GS)
techniques for power optimizations. We introduce a fast heuristic for choosing gates for
sizing and voltage scaling such that the total power is minimized under delay constraints.
We also use a more accurate estimate for determining the power dissipation of
the circuit by taking into account the short circuit power along with the dynamic power.
A better model of the short circuit power is used which takes into account the load
capacitance of the gates. Our results show that the combination of VS and GS perform
better than the techniques applied in isolation. An average power reduction of 73% is
obtained when decisions are taken assuming dynamic power only. In contrast, average
power reduction is 77% when decisons include the short circuit power dissipation.

Anshuman Nayak

Malay Haldar

Prith Banerjee

Chunhong Chen

Majid Sarrafzadeh

Power Optimization of Delay Constrained Circuits

We have studied quantum transport in both Si and GaAs interband tunneling diodes(ITD&#39;s). In the simulation, a non-equilibrium Green&#39;s function method based anempirical tight binding theory has been used to take into account evanescent-wavematching at interfaces and realistic band structures. Comparison has been madebetween the results of our multiband (MB) model and those of conventional two-band(2B) model. As a result, it is found that the current&#8211;voltage (I&#8211;V) characteristics of theSi ITD have considerably smaller peak current density than the conventional 2B model,since our MB model reflects correctly the indirect gap band structure. On the otherhand, in the GaAs ITD, there is small difference between the two models, becausetunneling occurs between the conduction band and the valence band at F point. It isalso found that the matching of evanescent electron modes is essentially necessary toinclude the valley-mixing effects at the tunneling interfaces.

Matsuto  Ogawa

Ryuichiro  Tominaga

Tanroku  Miyoshi

Tight Binding Simulation of Quantum Transportin Interband Tunneling Devices

The advantages of a Multi-Chip Module (MCM) product are its low-power and small-size.
But the design of an MCM system usually requires weeks of engineering effort, thus
we need a generic MCM substrate with programmable interconnections to accelerate
system prototyping. In this paper, we propose a Symmetric and Programmable MCM
(SPMCM) substrate for this purpose. This SPMCM substrate consists of a symmetrical
array of slots for bare-chip attachment and Field Programmable Interconnect Chips
(FPICs) for substrate routing. Experimental results demonstrate that our FPIC polygonal
routing module uses 12% less switches than the conventional routing module
for interconnecting bare-chip slots with 84 pads. Also, experiments are conducted to
determinate proper parameters for the VLSI implementation of our FPIC.

Mao-Hsu Yen

Sao-Jie Chen

Sanko H. Lan

Symmetric and Programmable Multi-Chip Module for Low-Power Prototyping System

A set of software tools for the determination of the band structure of zinc-blende,
wurtzite, 4H, and 6H semiconductors is presented. A state of the art implementation of
the nonlocal empirical pseudopotential method has been coupled with a robust simplex
algorithm for the optimization of the adjustable parameters of the model potentials.
This computational core has been integrated with an array of Matlab functions, providing
interactive functionalities for defining the initial guess of the atomic pseudopotentials,
checking the convergence of the optimization process, plotting the resulting
band structure, and computing detailed information about any local minimum.
The results obtained for wurtzite-phase III-nitrides (ALN, GaN, InN) are presented as a
relevant case study.

Enrico Ghillino

Carlo Garetto

Michele Goano

Giovanni Ghione

Enrico Bellotti

Kevin F. Brennan

Simplex Algorithm for Band Structure Calculation
of Noncubic Symmetry Semiconductors:
Application to III-nitride Binaries and Alloys

Placement of multiple dies on an MCM or high-performance VLSI substrate is a nontrivialtask in which multiple criteria need to be considered simultaneously to obtain atrue multi-objective optimization. Unfortunately, the exact physical attributes of adesign are not known in the placement step until the entire design process is carried out.When the performance issues are considered, crosstalk noise constraints in the formof net separation and via constraint become important. In this paper, for betterperformance and wirability estimation during placement for MCMs, several performanceconstraints are taken into account simultaneously. A graph-based wirabilityestimation along with the Genetic placement optimization technique is proposed tominimize crosstalk, crossings, wirelength and the number of layers. Our work issignificant since it is the first attempt at bringing the crosstalk and other performanceissues into the placement domain.

Jun Dong Cho

Jin Youn Cho

Deep-submicron Placement Minimizing Crosstalk

John  Barker

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VLSI Design