VLSI Design

Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs

Local Biasing and the Use of Nullator-Norator Pairs in Analog Circuits Designs

Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

Implementation of Hardware-Accelerated Scalable Parallel Random Number Generators

A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs

Error Immune Logic for Low-Power Probabilistic Computing

Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments

Post-CTS Delay Insertion

Emerging Carbon Nanotube Electronic Circuits, Modeling, and Performance

A SiGe BiCMOS Instrumentation Channel for Extreme Environment Applications

FPGA-Based Software Implementation of Series Harmonic Compensation for Single Phase Inverters

A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops

Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS

A Multilevel Congestion-Based Global Router

Floorplan-Driven Multivoltage High-Level Synthesis

VLSI Design

Table of Contents

Table of Contents

Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs

Local Biasing and the Use of Nullator-Norator Pairs in Analog Circuits Designs

Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

Implementation of Hardware-Accelerated Scalable Parallel Random Number Generators

A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs

Error Immune Logic for Low-Power Probabilistic Computing

Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments

Post-CTS Delay Insertion

Emerging Carbon Nanotube Electronic Circuits, Modeling, and Performance

A SiGe BiCMOS Instrumentation Channel for Extreme Environment Applications

FPGA-Based Software Implementation of Series Harmonic Compensation for Single Phase Inverters

A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops

Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS

A Multilevel Congestion-Based Global Router

Floorplan-Driven Multivoltage High-Level Synthesis