VLSI Design

A Signature-Based Power Model for MPSoC on FPGA

An Empirical Investigation on System and Statement Level Parallelism Strategies for Accelerating Scatter Search Using Handel-C and Impulse-C

Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm

Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms

Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method

A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies

A High-Throughput, High-Accuracy System-Level Simulation Framework for System on Chips

Vertical Gate RF SOI LIGBT for SPICs with Significantly Improved Latch-Up Immunity

Lossless and Low-Power Image Compressor for Wireless Capsule Endoscopy

Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications

Efficient Resource Sharing Architecture for Multistandard Communication System

Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies

Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection

CONTANGO: Integrated Optimization of SoC Clock Networks

VLSI Design

Table of Contents

Table of Contents

A Signature-Based Power Model for MPSoC on FPGA

An Empirical Investigation on System and Statement Level Parallelism Strategies for Accelerating Scatter Search Using Handel-C and Impulse-C

Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm

Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms

Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method

A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies

A High-Throughput, High-Accuracy System-Level Simulation Framework for System on Chips

Vertical Gate RF SOI LIGBT for SPICs with Significantly Improved Latch-Up Immunity

Lossless and Low-Power Image Compressor for Wireless Capsule Endoscopy

Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications

Efficient Resource Sharing Architecture for Multistandard Communication System

Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies

Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection

CONTANGO: Integrated Optimization of SoC Clock Networks