A second-order gm-C filter based on the Floating-Gate MOS (FGMOS) technique is presented. It uses a new fully differential transconductor and works at 2 V of voltage
supply with a full differential input linear range and a THD below 1%. Programming
and tuning are performed by means of a single voltage signal. The transconductor incorporates
a novel Common-Mode Feedback Circuit (CMFB) based also on FGMOS
transistors.

Esther O. Rodríguez-Villegas

Alberto Yúfera

Adoración Rueda

A Low-Voltage Floating-Gate MOS Biquad

A theoretical and computational analysis of the quantum dynamics of charge carriers in
presence of electron-phonon interaction based on the Wigner function is here applied to
the study of transport in mesoscopic systems. Numerical applications are shown for a) a
wave packet scattering with phonons while crossing a potential profile and b) electrons
scattering with phonons in a finite device with open boundary conditions.

C. Jacoboni

A. Abramo

P. Bordone

R. Brunetti

M. Pascoli

Application of the Wigner-Function Formulation to
Mesoscopic Systems in Presence of Electron-Phonon
Interaction

Field Programmable Gate Arrays (FPGAs) have a pre-defined chip boundary with fixed cell locations and routing resources. Placement objectives for flexible architectures (e.g., the standard cell design style) such as minimization of chip area do not reflect the primary placement goals for FPGAs. For FPGAs, the layout tools must seek 100% routability within the architectural constraints. Routability and congestion estimates must be made directly based on the demand and availability of routing resources for detailed routing of the particular FPGA. We. present a hierarchical placement approach consisting of two phases: a global placement phase followed by a detailed placement phase. The global placement phase minimizes congestion estimates of the global routing regions and satisfies all constraints at a coarser level. The detailed placer seeks to maximize the routability of the FPGA by considering factors which cause congestion at the detailed routing level and to precisely satisfy all of the constraints. Despite having limited knowledge about the gate level architectural details, we have achieved a 90%reduction in the number of unrouted nets in comparison to an industrial tool (the only other tool) developed specifically for this architecture.

Kalapi Roy

Bingzhong (David) Guan

Carl Sechen

A Sea-of-Gates Style FPGA Placement Algorithm

In this paper, a new optimization technique called SOFT(self-organizing fuzzy technique)
is proposed to solve the macro-cell placement problem. In SOFT, different criteria are
simultaneously accounted by a novel fuzzy gain function which models expert knowledge
to control the optimization process. The presented procedure is an adaptation of
Kohonen's self-organization algorithm which is well suited for implementation on
massively parallel architecture for fast computing. The MCNC benchmark examples are
presented to verify the performance and feasibility of SOFT. Comparisons are made
with the Hopfield network, SOAP and TimberWolf MC5.6. Experiments show that the
proposed method yields an average of 17% improvement in total wire length compared
with previous methods. Large size problems with 225 and 1024 arbitrarily-sized macrocells
are also presented.

Ray-I Chang

Pei-Yung Hsiao

Macro-Cell Placement for Custom-Chip Design Using Self-Organizing Fuzzy Technique

Recent experiments on the formation of crystalline CO2 from a newly discovered binary
phase consisting of CO2 and C2H2 at 90° K fail to be adequately simulated by Avrami
equations. The purpose of this note is to develop an alternative to the Avrami model
which can make accurate predictions for these experiments. The new model uses empirical
approximations to the distribution densities of the volumes of three-dimensional
Voronoi cells defined by Poisson-generated crystallization kernels (nuclei). Inside each
Voronoi cell, the growth of the crystal is assumed to be linear in diameter (i.e., cubic in
volume) until the cell is filled by the CO2 crystals and the C2H2 (thought of as a waste
product). The cumulative growth curve is computed by averaging these individual growth
curves with respect to the distribution density of the volumes of the Voronoi cells. Agreement
with the experiments is excellent.

Terry Gough

Reinhard Illner

Modeling Crystallization Dynamics when the Avrami Model Fails

We present an analytical model for the I–V characteristics of a single-electron transistor,
which may be incorporated in a conventional circuit simulator, such as SPICE. Our model
takes as its input the physical SET characteristics (capacitances and tunnel resistances,
which may be determined experimentally), and it yields I–V curves which are in excellent
agreement with the ones obtained from full-scale Monte Carlo simulations.

Xiaohui Wang

Wolfgang Porod

Analytic I–V Model for Single-Electron Transistors

Using the finite element method, we investigate device applications of lateral resonant tunneling
structures which consist of a transmission channel with attached resonators. Such
structure exhibits resonance-antiresonance transmission features which may be engineered to
achieve desired device properties.
We show that the valley current can be reduced in such 2D lateral resonant tunneling
devices, resulting in an improved current peak-to-valley ratio.

Zhi-An Shao

Craig S. Lent

2D Finite Element Method Simulation of Lateral Resonant Tunneling Devices

In recent years, substantial advances have been made in understanding hydrodynamic
models, both from the standpoint of analytical infrastructure, as well as the parameters
which play a decisive effect in the behavior of such models. Both classical and quantum
hydrodynamic models have been studied in depth. In this survey paper, we describe
several results of this type. We include, for example, well-posedness for both classical
and quantum reduced models, and the relaxation drift–diffusion limit as examples of
analytical results. As examples of computational results, we include some discussion of
effective algorithms, but most importantly, some information gleaned from extensive
simulation. In particular, we present our findings of the prominent role played by the
mobilities in the classical models, and the role of hysteresis in the quantum models. All
models are self-consistent. Included is discussion of recent analytical results on the use
of Maxwell’s equations. Benchmark devices are utilized: the MESFET transistor and
the n+/n/n+ diode for classical transport, and the resonant tunneling diode for quantum
transport. Some comparison with the linear Boltzmann transport equation is included.

Joseph W. Jerome

Analytical and Computational Advances for Hydrodynamic
Models of Classical and Quantum Charge Transport

In the past ten years, many researchers have focused attention on developing better data structures for storing graphical information. Among the proposed data structures, the quad tree data structure provides a good way to organize objects on a 2-D plane. Region searches proceed at logarithmic speeds a desirable characteristic, but no previously proposed VLSI quad tree data structure distributed objects to subdivide the spatial area. This has been a major drawback for operations such as tree searching and window query. In this paper, we present a new division method to reconstruct those quad trees including the multiple storage quad tree (MSQT) and the quad list quad tree (QLQT) into nearly balanced quad tree data structures. Nearly balanced quad trees based on our new spatial division method are constructed by dynamically translating unbalanced multiple storage quad trees or unbalanced quad list quad trees into balanced structures. All benefits of the original quad tree data structures are completely retained. In addition, this method is simple and balanced quad trees memory require less than the original quad trees. Experimental results illustrate that the improvement in region queries of the presented nearly balanced quad trees to both of the QLQT and the MSQT is better than the improvement of the QLQT to the MSQT.

Pei-Yung  Hsiao

Nearly Balanced Quad List Quad Tree -A Data Structure for VLSI Layout Systems

Given a set of terminals on the plane <mml:math id="E1" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>N</mml:mi><mml:mo>=</mml:mo><mml:mrow><mml:mo>{</mml:mo><mml:mrow><mml:mi>s</mml:mi><mml:mo>,</mml:mo><mml:msub><mml:mi>ν</mml:mi><mml:mn>1</mml:mn></mml:msub><mml:mo>,</mml:mo><mml:mo>…</mml:mo><mml:mo>,</mml:mo><mml:msub><mml:mi>ν</mml:mi><mml:mi>n</mml:mi></mml:msub></mml:mrow><mml:mo>}</mml:mo></mml:mrow></mml:math>, with a source terminal s, a
Rectilinear Distance-Preserving Tree (RDPT) T(V, E) is defined as a tree rooted at s,
connecting all terminals in N. An RDPT has the property that the length of every source
to sink path is equal to the rectilinear distance between that source and sink. A Min-
Cost Rectilinear Distance-Preserving Tree (MRDPT) minimizes the total wire length
while maintaining minimal source to sink linear delay, making it suitable for high
performance interconnect applications.This paper studies problems in the construction of RDPTs, including the following
contributions. A new exact algorithm for a restricted version of the problem in one
quadrant with O<mml:math id="E2" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mo>(</mml:mo><mml:mrow><mml:msup><mml:mi>n</mml:mi><mml:mn>2</mml:mn></mml:msup></mml:mrow><mml:mo>)</mml:mo></mml:mrow></mml:math> time complexity is proposed. A novel heuristic algorithm, which
uses optimally solvable sub-problems, is proposed for the problem in a single quadrant.
The average and worst-case time complexity for the proposed heuristic algorithm are O<mml:math id="E3" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mo>(</mml:mo><mml:mrow><mml:msup><mml:mi>n</mml:mi><mml:mrow><mml:mrow><mml:mn>3</mml:mn><mml:mo>/</mml:mo><mml:mn>2</mml:mn></mml:mrow></mml:mrow></mml:msup></mml:mrow><mml:mo>)</mml:mo></mml:mrow></mml:math> and O<mml:math id="E4" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mo>(</mml:mo><mml:mrow><mml:msup><mml:mi>n</mml:mi><mml:mn>3</mml:mn></mml:msup></mml:mrow><mml:mo>)</mml:mo></mml:mrow></mml:math>, respectively. A 2-approximation of the quadrant merging problem is proposed. The proposed algorithm has time complexity <mml:math id="E5" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>O</mml:mi><mml:mrow><mml:mo>(</mml:mo><mml:mrow><mml:msup><mml:mi>α</mml:mi><mml:mn>2</mml:mn></mml:msup><mml:mi>T</mml:mi><mml:mrow><mml:mo>(</mml:mo><mml:mi>n</mml:mi><mml:mo>)</mml:mo></mml:mrow><mml:mo>+</mml:mo><mml:msup><mml:mi>α</mml:mi><mml:mn>3</mml:mn></mml:msup></mml:mrow><mml:mo>)</mml:mo></mml:mrow></mml:math> for any constant
α &gt; 1, where T(n) is the time complexity of the solution of the RDPT problem on one
quadrant. This result improves over the best previous quadrant merging solution which
has <mml:math id="E6" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>O</mml:mi><mml:mrow><mml:mo>(</mml:mo><mml:mrow><mml:msup><mml:mi>n</mml:mi><mml:mn>2</mml:mn></mml:msup><mml:mi>T</mml:mi><mml:mrow><mml:mo>(</mml:mo><mml:mi>n</mml:mi><mml:mo>)</mml:mo></mml:mrow><mml:mo>+</mml:mo><mml:msup><mml:mi>n</mml:mi><mml:mn>3</mml:mn></mml:msup></mml:mrow><mml:mo>)</mml:mo></mml:mrow></mml:math> time complexity.We test our algorithms on randomly uniform point sets and compare our heuristic
RDPT construction against a Minimum Cost Rectilinear Steiner (MRST) tree
approximation algorithm. Our results show that RDPTs are competitive with Steiner
trees in total wire-length when the number of terminals is less than 32. This result makes
RDPTs suitable for VLSI routing applications. We also compare our algorithm to the
Rao-Shor RDPT approximation algorithm obtaining improvements of up to 10% in
total wirelength. These comparisons show that the algorithms proposed herein produce
promising results.

Gustavo E. Téllez

Majid Sarrafzadeh

On Rectilinear Distance-Preserving Trees

The reconfigurable mesh (RN-MESH) can solve a large class of problems in constanttime, including problems that require logarithmic time by other, even shared memory,models such as the PRAM with a similar number of processors [3]. In this work we showthat for the RN-MESH these constants can always be reduced to one, still using apolynomial number of processors. Given a reconfigurable mesh that computes a set ofvalues in constant time, we show that it can be simulated by a single step reconfigurablemesh with maximum size that is polynomial in the size of the original mesh. The proof isconstructive, where the construction of the single step RN-MESH holds for therelatively weak undirected RN-MESH model. In this model broadcasts made on busesarrive at all nodes that belong to the undirected connected component of thetransmitting processor. A result similar to the one that is obtained in this work waspreviously obtained for the directed reconfigurable mesh model (DRN) [5]. However,the construction for the DRN-MESH relies on the fact that the buses are directed, andthus cannot be applied to the undirected case. In addition, the construction presentedhere is simpler and uses significantly fewer processors than the one obtained for theDRN-MESH.

Yosi  Ben-Asher

Assaf  Schuster

Single Step Undirected Reconfigurable Networks

The generalized tunneling formula with the simple model for the broadening in the contactsgives surprisingly good results for the majority of RTD structures. It is just as fast as thestandard coherent tunneling simulators and much more versatile. It is easily generalized tomulti-band and multidimensional models. The multi-band generalization of the theory and theeffect of the optical potential are described.

R.  Lake

G.  Klimeck

R. C. Bowen

D.  Jovanovic

P.  Sotirelis

W. R. Frensley

A Generalized Tunneling Formula for Quantum Device Modeling

Electron transport in model Si nanotransistors is examined by numerical simulation
using a hierarchy of simulation methods, from full Boltzmann, to hydrodynamic, energy
transport, and drift-diffusion. The on-current of a MOSFET is shown to be limited by
transport across a low-field region about one mean-free-path long and located at the beginning
of the channel. Commonly used transport models based on simplified solutions
of the Boltzmann equation are shown to fail under such conditions. The cause for
this failure is related to the neglect of the carriers' drift energy and to the collision-dominated
assumptions typically used in the development of simplified transport
models.

Kausar Banoo

Jung-Hoon Rhew

Mark Lundstrom

Chi-Wang Shu

Simulating Quasi-ballistic Transport
in Si Nanotransistors

Although impact ionization feedback is recognized as an important current multiplicationmechanism, its importance as a carrier heating mechanism has been largelyoverlooked. This work emphasizes the inclusion of impact ionization feedback in MonteCarlo device simulations, and its implications for carrier heating in sub-micron CMOSand EEPROM technologies.

Jeff D. Bude

Monte Carlo Simulations of Impact Ionization Feedback in MOSFET Structures

An automatic logic/circuit synthesizer is developed which takes several Boolean functions as input and generates netlist output with basic composing cells from the pass-transistor cell library containing only two types of cells: 2-to-1 multiplexers and inverters. The synthesis procedure first constructs efficient binary decision diagrams (BDDs) for these Boolean functions considering both multi-function sharing and minimum width. Each node in the BDD trees is realized by using a 2-to-1 multiplexer (MUX) of proper driving capability designed pass-transistor logic. The inverters are then inserted all along the MUX paths in order to improve the speed performance and to alleviate the voltage-drop problem. Several methods are proposed to reduce the critical path delay in the multiplexer-chains for generation of faster circuits. Compared to the recently proposed pass-transistor-based top-down design, our synthesizer has better speed and area performance due to the reduced number of cascaded inverters.

Shen-Fu  Hsiao

Jia-Siang  Yeh

Da-Yen  Chen

High-performance Multiplexer-based Logic Synthesis Using Pass-transistor Logic

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