In FPGAs the routing resources are fixed and their usage is constrained by the locationof antifuses. In addition, the antifuses affect the layout performance significantly,depending on the technology. Hence, simplistic placement level assumptions turn out tobe grossly inadequate in predicting the timing and wirability behavior of a layout.There is a need, therefore, for a layout technique which changes the layout at placementlevel based on accurate post-layout timing analysis and net wirability. In this paper weconsider such a wirability and performance driven layout flow for row-based FPGAs.Timing information from a post-layout timing analyzer and wirability informationfrom global and channel routers are used by an incremental placer to effectively perturbthe placement. A large improvement (up to 29&#37;) in timing, has been obtained(compared to non-iterative FPGA layout) for a set of industrial designs and benchmarkexamples.

Sudip  Nag

Kaushik  Roy

Performance and Wirability Driven Layout for Row-Based FPGAs

One of the major problems within the VHDL based behavioral synthesis is to start the design on higher abstraction level than the register transfer level (RTL). VHDL semantics was designed strictly for simulation, therefore it was not considered as high-level synthesis language. A novel synthesis procedure was developed, which uses the methodology of high level synthesis. It starts from an abstract VHDL model and produces an RTL VHDL description through successive language transformations while preserving the VHDL standard simulation semantics. The steps of the synthesis do not use graph representation or other meta-language, but apply the standard VHDL only. This VHDL representation is simulatable and accessible, functional verification can be performed by simulation at any time, and the simulation results can be used to guide the synthesis process. The output VHDL format is suitable to continue the design flow with RTL based synthesis tools.

László Varga

Gábor Hosszú

Ferenc Kovács

Design Procedure Based on VHDL Language Transformations

Least Common Ancestor Networks (LCANs) are introduced and shown to be a class of networks that include fattrees,baseline networks, SW-banyans and the router networks of the TRAC 1.1 and 2.0 and the CM-5. SomeLCAN properties are stated and the circuit-switched permutation routing capabilities of an important subclass areanalyzed. Simulation results for three permutation classes verify the accuracy of an iterative analysis for a randomizedrouting strategy. These results indicate that the routing strategy provides highly predictable router performancefor all permutations. An off-line routing algorithm is also given, and it is shown how to realize certain classes ofpermutations by adapting Nassimi and Sahni&#39;s, and Raghavendra and Boppana&#39;s self-routing algorithms for Benesnetworks.

Isaac D. Scherson

Chi-Kai  Chien

Least Common Ancestor Networks

In this paper, a new low power design method of the FIR filter for image processing isproposed. Because the correlation between adjacent pixels is very high in image data,the clock gating technique can be a good candidate for low power strategy. However,the conventional clock gating strategy that is applied independently to every flip-flopof the filter give rise to too much additional area overhead and couldn&#39;t get a good resultin the power reduction. In our method, each tap register, which is used to delay theinput data in the filter, is partitioned into two sub-registers according to the correlationcharacteristic of its input space. For the sub-register which highly correlated data isinputted into, the dynamic power consumption is reduced by diminishing switchingactivity of the clock signal. We can also reduce the additional hardware overhead bypropagating the clock gating control signal of the first tap register to other tap registers.To identify the efficiency of the proposed design method, we perform the experiments onsome filters that are designed in VHDL. The power estimation tool says that theproposed method can reduce the power dissipation of the filter by more than 18&#37;compared to the conventional filter design methods.

Jun Mo Jung

Jong-Wha  Chong

A Low Power FIR Filter Design for Image Processing

Dinesh  Bhatia

Field-Programmable Gate Arrays

We describe a newly developed parallel three-dimensional semiconductor device simulator.The program utilizes the message passing architecture and has been developed on a networkof workstations. Two iterative algorithms to solve the nonlinear semiconductor device equationsare presented. The algorithms are tested by simulating a three-dimensional MOSFETstructure. A near-ideal speedup for the distributed algorithms has been obtained for Poisson’sequation.

Mei-Kei  Ieong

Ting-Wei  Tang

Distributed Algorithms for Three-dimensionalSemiconductor Device Simulations

We show an existence and uniqueness result for mildly nonlinear Schrödinger systems of
(self-consistent) Hartree–Fock form. We also shortly resume the already existing results
on the semiclassical limit and the asymptotic and dispersive behavior of such systems.

I. Gasser

On Hartree–Fock Systems

In this article we concisely present several modern strategies that are applicable to driftdominated
carrier transport in higher-order deterministic models such as the driftdiffusion,
hydrodynamic, and quantum hydrodynamic systems. The approaches include
extensions of “upwind” and artificial dissipation schemes, generalization of the traditional
Scharfetter – Gummel approach, Petrov – Galerkin and streamline-upwind Petrov
Galerkin (SUPG), “entropy” variables, transformations, least-squares mixed methods
and other stabilized Galerkin schemes such as Galerkin least squares and discontinuous
Galerkin schemes. The treatment is representative rather than an exhaustive
review and several schemes are mentioned only briefly with appropriate reference
to the literature. Some of the methods have been applied to the semiconductor device
problem while others are still in the early stages of development for this class of applications.
We have included numerical examples from our recent research tests with
some of the methods. A second aspect of the work deals with algorithms that employ
unstructured grids in conjunction with adaptive refinement strategies. The full benefits
of such approaches have not yet been developed in this application area and we
emphasize the need for further work on analysis, data structures and software to
support adaptivity. Finally, we briefly consider some aspects of software frameworks.
These include dial-an-operator approaches such as that used in the industrial simulator
PROPHET, and object-oriented software support such as those in the SANDIA
National Laboratory framework SIERRA.

Graham F. Carey

A. L. Pardhanani

S. W. Bova

Advanced Numerical Methods and Software Approaches
for Semiconductor Device Simulation

This paper presents a methodology and a tool box for system-level partitioning in the behavioral domain. The methodologyis based on an extended finite state machine model. Partitioning is achieved interactively through the application of fivesystem-level transformation primitives: MOVE, MERGE, SPLIT, CUT and MAP. This scheme allows an interactiveexploration of the solution space. The result of the partitioning is a set of interconnected and heterogeneous sub-systems.The partitioning tool box which has been developed is named PARTIE PARTIF includes an evaluation feedback loop thathelps the designer estimate the quality of the design.

Tarek Ben Ismail

Kevin   O&#39;Brien

Ahmed  Jerraya

PARTIF: Interactive System-level Partitioning

In this paper we present an approach for combining on-line concurrent checking (CC)
with off-line built-in self-test (BIST). We will show that a reduction of an aliasing
probability can be obtained for manufacturing testing by monitoring the output of a
concurrent checker and a reduction of a probability of not detecting an error in the
computing mode can be obtained by a short periodic BIST. We will present a technique
for optimal selection of error-detecting codes for combined on-line CC and off-line
space-time compression of test responses for BIST and estimate probabilities of not
detecting an error for the approach based on integrating CC and BIST. We also present a
technique for on-line error-detection in space-time compressors of test responses for
BIST.

Mark G. Karpovsky

Integrated On-Line and Off-Line Error Detection
Mechanisms in the Coding Theory Framework

In the context of 2-D and 3-D unstructured mixed-element meshes, a new method of recoveringvectorial fields and currents in multidimensional simulation is introduced. The newmethod, called the method of edge elements, directly interpolates the projections of the vectorson the edges of an element into its interior. The new method is compared to two otherrecovery methods on the basis of resolution, consistency, and implementation ease.

Daniel C. Kerr

Isaak D. Mayergoyz

A New Method to Recover Vectorial Electric Fields andCurrent Densities from Unstructured Meshes

A new hypercube-like topology, called the hyper Petersen (HP) network, is proposed and analyzed, which isconstructed from the well-known cartesian product of the binary hypercube and the Petersen graph of ten nodes.This topology is an attractive candidate for multiprocessor interconnection having such desirable properties asregularity, high symmetry and connectivity, and logarithmic diameter. For example, an n-dimensional hyper Petersennetwork, <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>H</mml:mi><mml:msub><mml:mi>P</mml:mi><mml:mi>n</mml:mi></mml:msub></mml:mrow></mml:math>, with N&#61;1.25 * <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msup><mml:mn>2</mml:mn><mml:mi>n</mml:mi></mml:msup></mml:mrow></mml:math> nodes is a regular graph of degree and node-connectivity n and diameter n&#8211;1, whereas an (n&#8211;1)-dimensional binary hypercube, <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>Q</mml:mi><mml:mrow><mml:mi>n</mml:mi><mml:mo>&#x2212;</mml:mo><mml:mn>1</mml:mn></mml:mrow></mml:msub></mml:mrow></mml:math>, with the same diameter covers only <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msup><mml:mn>2</mml:mn><mml:mrow><mml:mi>n</mml:mi><mml:mo>&#x2212;</mml:mo><mml:mn>1</mml:mn></mml:mrow></mml:msup></mml:mrow></mml:math> nodes, eachof degree (n&#8211;1). Thus the HP topology accommodates 2.5 times extra nodes than <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>Q</mml:mi><mml:mrow><mml:mi>n</mml:mi><mml:mo>&#x2212;</mml:mo><mml:mn>1</mml:mn></mml:mrow></mml:msub></mml:mrow></mml:math> at the cost of increasingthe node-degree by one. With the same degree and connectivity of n, the diameter of the <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>H</mml:mi><mml:msub><mml:mi>P</mml:mi><mml:mi>n</mml:mi></mml:msub></mml:mrow></mml:math> network is one lessthan that of <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>Q</mml:mi><mml:mi>n</mml:mi></mml:msub></mml:mrow></mml:math>, yet having 1.25 times larger number of nodes.Efficient routing and broadcasting schemes are presented, and node-disjoint paths in <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>H</mml:mi><mml:msub><mml:mi>P</mml:mi><mml:mi>n</mml:mi></mml:msub></mml:mrow></mml:math>, are computed evenunder faulty conditions. The versatility of the hyper Petersen networks is emphasized by embedding rings, meshes,hypercubes and several tree-related topologies into it. Contrary to the hypercubes, rings of odd lengths, and acomplete binary tree of height n&#8211;1 permit subgraph embeddings in <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>H</mml:mi><mml:msub><mml:mi>P</mml:mi><mml:mi>n</mml:mi></mml:msub></mml:mrow></mml:math>.

Sajal K. Das

Sabine  &#214;hring

Amit K. Banerjee

Embeddings into Hyper Petersen Networks: YetAnother Hypercube-Like Interconnection Topology

The layout of a circuit can influence the probability of occurrence of faults. In this
paper, we develop algorithms that can take advantage of this fact to reduce the chances
of hard-to-detect (HTD) faults from occurring. We primarily focus on line bridge faults
in this paper. We define a bridge fault f as an HTD fault if an automatic test pattern
generator fails to generate a test vector for f in a reasonable amount of CPU-time. It is
common practice to drop such HTD faults from consideration during test generation.
The chip fault coverage achieved by a test set is poor if the fault set consists of many
HTD faults. We can combat this problem by avoiding altogether, or by reducing the
probability of, the occurrence of HTD faults. In this paper, we consider hard-to-detect
bridging faults and show how module placement rules can be derived to reduce the
probability of these faults. A genetic placement algorithm that optimizes area while
respecting these rules is presented. The placement algorithm has been implemented for
standard-cell layout style on a SUN/SPARC and tested against several sample circuits.

C. P. Ravikumar

Nikhil Sharma

Testability-Driven Layout of Combinational Circuits

Inner product calculations are often required in digital neural computing. The criticalpath of the inner product of two binary vectors is the carry propagation delay generatedfrom individual product terms. In this work, two architectures to arrange digital ratioedcompressors are presented to reduce the carry propagation delay in the critical path.Besides, the carry propagation delay estimation of these compressor building blocks isderived and compared. The theoretical analysis and Verilog simulation both indicatethat one of the compressor building blocks we present here might offer a sub-optimalsolution for the basic building blocks used in digital hardware realization of the innerproduct computation.

Chua-Chin  Wang

Chenn-Jung  Huang

Po-Ming  Lee

Design and Analysis of Digital Ratioed Compressors for Inner Product Processing

We present a design method (called STD architecture) to design large memories so that the test time does notincrease with the increasing size of memory. Large memories can be constructed by using several small blocksof memory. The memory address decoder is divided into two or more levels and designed such that during thetest mode all small memory blocks are accessed together. With the help of modified decoder, all small memoryblocks are tested in parallel using any standard test algorithm. In this design, time to test the whole memory isequal to the time required to test one small block. The proposed design is highly structured and hardware overheadis negligible. The basic idea is to exploit internal hardware for testing purpose. With the proposed method aconstant test time can be achieved irrespective of the memory size. STD architecture is applicable to memorychips as well as memory boards, and the design is suitable for fault detection as well as for fault diagnosis.

Rochit  Rajsuman

Kamal  Rajkanan

STD Architecture: A Practical Approach to TestM-Bits Random Access Memories

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VLSI Design