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VLSI Design

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Table of Contents

Table of Contents

  • VLSI Design -
  • Special Issue
  • Volume 2
  • - Article ID 090841

High Throughput Error Control Using Parallel CRC

Andrzej Sobski | Alexander Albicki
  • VLSI Design -
  • Special Issue
  • - Volume 10
  • - Article ID 038974

Tuning Strategies for Global Interconnects in High-Performance Deep-Submicron ICs

Andrew B. Kahng | Sudhakar Muddu | Egino Sarto
  • VLSI Design -
  • Special Issue
  • Volume 5
  • - Article ID 010797

A Greedy Algorithm for Over-The-Cell Channel Routing

Gudni Gudmundsson | Simeon Ntafos
  • VLSI Design -
  • Special Issue
  • - Volume 11
  • - Article ID 042016

Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-checking Circuits

Cecilia Metra | Michele Favalli | Bruno Riccò
  • VLSI Design -
  • Special Issue
  • Volume 3
  • - Article ID 023249

An ILP Solution for Optimum Scheduling, Module and Register Allocation, and Operation Binding in Datapath Synthesis

T. C. Wilson | N. Mukherjee | ... | D. K. Banerji
  • VLSI Design -
  • Special Issue
  • Volume 14
  • - Article ID 764061

Generalized Inclusive Forms—New Canonical Reed-Muller Forms Including Minimum ESOPs

Malgorzata Chrzanowska-Jeske | Alan Mishchenko | Marek Perkowski
  • VLSI Design -
  • Special Issue
  • Volume 12
  • - Article ID 050167

A Universal, Dynamically Adaptable and Programmable Network Router for Parallel Computers

Taras I. Golota | Sotirios G. Ziavras
  • VLSI Design -
  • Special Issue
  • - Volume 9
  • - Article ID 081341

Dispersion Lemmas Revisited

I. Gasser | P. A. Markowich | B. Perthame
  • VLSI Design -
  • Special Issue
  • - Volume 1
  • - Article ID 039791

Integrated Test Solutions for a System Design Environment

Kevin T. Kornegay | Robert W. Brodersen
  • VLSI Design -
  • Special Issue
  • Volume 7
  • - Article ID 014757

On Ensuring Multilayer Wirability by Stretching Layouts

Teofilo F. Gonzalez | Si-Qing Zheng
  • VLSI Design -
  • Special Issue
  • Volume 11
  • - Article ID 076384

An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization

Chaeryung Park | Taewhan Kim | C. L. Liu
  • VLSI Design -
  • Special Issue
  • Volume 14
  • - Article ID 132807

A Noise-shaping Accelerometer Interface Circuit for Two-chip Implementation

Tetsuya Kajita | Un-Ku Moon | Gabor C. Temes
  • VLSI Design -
  • Special Issue
  • - Volume 3
  • - Article ID 031829

Decomposition and Reduction: General Problem-Solving Paradigms

Michal Servít | Jan Zamazal
  • VLSI Design -
  • Special Issue
  • - Volume 4
  • - Article ID 045983

Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays

Stephen Brown | Muhammad Khellah | Guy Lemieux
  • VLSI Design -
  • Special Issue
  • Volume 6
  • - Article ID 051378

Quadrilateral Finite Element Monte Carlo Simulation of Complex Shape Compound FETs

S. Babiker | A. Asenov | ... | S. P. Beaumont

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