Quantum transport is becoming more significant as device size shrinks. For example, asdevice sizes are scaled below 0.1 &#956;m, the number of impurities becomes quite small, sothat they are no longer homogeneously distributed throughout the device volume andthe carriers are localized into quantum boxes, in that self-energy corrections produced bylocally high carrier densities will lead to quantum dot formation. This leads to the needto discuss transport through an array of such quantum structures. Here, we discussseveral issues which must be considered in treating the transport through such devices.

D. K. Ferry

J. R. Barker

Open Problems in Quantum Simulationin Ultra-Submicron Devices

We propose a VLSI inner product processor architecture involving broadcasting only over short buses (containing less than 64 switches). The architecture leads to an efficient algorithm for the inner product computation. Specifically, it takes 13 broadcasts, each over less than 64 switches, plus 2 carry-save additions <mml:math id="E1" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mo>(</mml:mo><mml:mrow><mml:msub><mml:mi>t</mml:mi><mml:mrow><mml:mi>c</mml:mi><mml:mi>s</mml:mi><mml:mi>a</mml:mi></mml:mrow></mml:msub></mml:mrow><mml:mo>)</mml:mo></mml:mrow></mml:math> and 2 carry-lookahead additions <mml:math id="E2" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mo>(</mml:mo><mml:mrow><mml:msub><mml:mi>t</mml:mi><mml:mrow><mml:mi>c</mml:mi><mml:mi>l</mml:mi><mml:mi>a</mml:mi></mml:mrow></mml:msub></mml:mrow><mml:mo>)</mml:mo></mml:mrow></mml:math> to compute the inner product of two arrays of <mml:math id="E3" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>N</mml:mi><mml:mo>=</mml:mo><mml:msup><mml:mn>2</mml:mn><mml:mn>9</mml:mn></mml:msup></mml:math> elements, each consisting of <mml:math id="E4" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>m</mml:mi><mml:mo>=</mml:mo><mml:mn>64</mml:mn></mml:math> bits. Using the same order of VLSI area, our algorithm runs faster than the best known fast inner product algorithm of Smith and Torng [“Design of a fast inner product processor,” Proceedings of IEEE 7th Symposium on Computer Arithmetic (1985)], which takes about 28 <mml:math id="E5" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:msub><mml:mi>t</mml:mi><mml:mrow><mml:mi>c</mml:mi><mml:mi>s</mml:mi><mml:mi>a</mml:mi></mml:mrow></mml:msub></mml:math> + <mml:math id="E6" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:msub><mml:mi>t</mml:mi><mml:mrow><mml:mi>c</mml:mi><mml:mi>l</mml:mi><mml:mi>a</mml:mi></mml:mrow></mml:msub></mml:math> for the computation.

R. Lin

S. Olariu

Fast Inner Product Computation on Short Buses

As MOSFETs are scaled to deep submicron dimensions non-equilibrium, near ballistic,
transport in p-MOSFETs becomes important. Recent experimental data indicates that
as MOSFETs are scaled the performance gap between n and p-channel shrinks. Nonequilibrium
transport effects and performance potentials of ‘Well Tempered’ Si p-
MOSFETs with gate lengths of 50 and 25 nm are studied. Monte Carlo and calibrated
Drift Diffusion simulations of these devices provide a quantitative estimate of the
importance and the influence of non-equilibrium transport on submicron device
performance. A possible explanation for the closing performance gap between n- and
p-channel MOSFETs is offered.

J. R. Watling

Y. P. Zhao

A. Asenov

Non-Equilibrium Hole Transport in Deep Sub-Micron
Well-Tempered Si p-MOSFETs

A simplified method for characterization of standard library cells based on the linear delay model is presented in this paper. The linear model is chosen as it allows rapid characterization with a modest number of simulations, while achieving acceptable accuracy. All the parameters of cell delays are defined as 50&#37;-to-50&#37; delays, as distinguished from 50&#37;-to-threshold or threshold-to-50&#37; often used in commercial tools. We found that the 50&#37;-to-50&#37; definition of delays is more consistent and leads to closed-form formula. A subset of library cells in a 0.25 &#956;m technology was characterized using the proposed technique. A test circuit was subsequently generated and simulated to determine the accuracy of the proposed characterization method. SPICE simulations on the test circuit show that the timing estimations obtained through the proposed method is accurate to within 5.6&#37;, and the power estimation was accurate to 4.2&#37;, ignoring parasitics on interconnections.

Jos B. Sulistyo

Dong S. Ha

A New Characterization Method for Delay and Power Dissipation of Standard Library Cells

The “smooth” quantum hydrodynamic (QHD) model is derived specifically to handle
in a mathematically rigorous way the discontinuities in the classical potential energy
which occur at heterojunction barriers in quantum semiconductor devices. Smooth QHD
model simulations of the resonant tunneling diode are presented which exhibit enhanced
negative differential resistance when compared with simulations using the original O(ħ2)
QHD model. In addition, smooth QHD simulations of a classical electron shock wave are
presented which agree with classical hydrodynamic model simulations and which do not
exhibit the spurious dispersive oscillations of the O(ħ2) QHD model.

Carl L. Gardner

Theory and Simulation of the Smooth Quantum
Hydrodynamic Model

A highly regular parallel multiplier architecture along with the novel low-power, high-performanceCMOS implementation circuits is presented. The superiority is achievedthrough utilizing a unique scheme for recursive decomposition of partial productmatrices and a recently proposed non-binary arithmetic logic as well as thecomplementary shift switch logic circuits.The proposed 64&#215;64-b parallel multiplier possesses the following distinct features:(1) generating 64 8&#215;8-b partial product matrices instead of a single large one; (2)comprising only four stages of bit reductions: first, by 8&#215;8-b small parallel multipliers,then, by small parallel counters in each of the remaining three stages. A family of shiftswitch parallel counters, including non-binary (6, 3)&#8727; and complementary (k, 2) for2 &#8804; k &#8804; 8, are proposed for the efficient bit reductions; (3) using a simple final adder.The non-binary logic operates 4-bit state signals (representing integers ranging from(0 to 3), where no more than half of the signal bits are subject to value-change at anylogic stage. This and others including minimum transistor counts, fewer inverters, andlow-leakage logic structure, significantly reduce circuit power dissipation.

Rong  Lin

A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic Counter Circuits

Built-in-self-test (BIST) response data can be compacted using a linear-feedback shift register (LFSR). Prior workhas indicated that the probability of aliasing tends to converge to 2-k for a polynomial of degree k and large testlength, and that primitive polynomials perform better than non-primitive polynomials. Nearly all analytical modelsand simulations have been based on the assumption that error occurrences are statistically-independent. Thispaper presents the first statistical results, based on fault simulation, that show that this convergence propertyholds for actual digital logic circuits and randomly-generated test vector sequences. However, it is shown thatthe average probability of aliasing is unsuitable as a design metric, and that a 95&#37; upper confidence limit (UCL)is more useful. This paper introduces a UCL for the loss of fault coverage due to test response compaction. Thetheoretical or &#8220;ideal&#8221; UCL is shown to match closely the empirically-derived UCL obtained by fault simulation.The result is that a tight lower bound on fault coverage for LFSR-based BIST configurations can be obtainedeasily. Fault coverage for a BIST configuration can be obtained without the LFSR, eliminating costly faultsimulation of the full structure with the LFSR. These results have been incorporated in the standard procedurefor fault coverage measurement.

Warren H. Debany

Mark J. Gorniak

Anthony R. Macera

Daniel E. Daskiewich

Kevin A. Kwiat

Heather B. Dussault

Empirical Bounds on Fault Coverage LossDue to LFSR Aliasing

Although SRT division and square-root approaches and GST division approach havebeen known for long time, square-root architectures based on the GST approach havenot been proposed so far which do not require a final division/multiplication of the scalefactor. A GST square-root architecture is developed without requiring either amultiplication to update the scaled square-root quotient in each iteration or a division/multiplication by the scaling factor after completing the square-root iterations.Additionally, quantitative comparison of speed and power consumption of GST andSRT division/square-root units are presented. Shared divider and square-root units aredesigned based on the SRT and the GST approaches, in minimally and maximallyredundant radix-4 representations. Simulations demonstrate that the worst-case overalllatency of the minimally-redundant GST architecture is 35&#37; smaller compared to theSRT. Alternatively, for a fixed latency, the minimally-redundant GST architecturebased division and square-root operations consume 32&#37; and 28&#37; less power,respectively, compared to the maximally-redundant SRT approach.

Martin  Kuhlmann

Keshab K. Parhi

A Novel Low-power Shared Division and Square-root Architecture Using the GST Algorithm

A novel scheme to compute energy on-the-fly and thereby control the quality of the image frames dynamically is presented along with its FPGA implementation. This scheme is suitable for incorporation in image compression systems such as video encoders. In this new scheme, processing is automatically stopped when the desired quality is achieved for the image being processed by using a concept called pruning. Pruning also increases the processing speed by a factor of more than two when compared to the conventional method of processing without pruning. An MPEG-2 encoder implemented using this scheme is capable of processing good quality monochrome and color images of sizes up to 1024 &#215; 768 pixels at the rate of 42 and 28 frames per second, respectively, with a compression ratio of over 17:1. The encoder is also capable of working in the fixed pruning level mode with user programmable features.

S.  Ramachandran

S.  Srinivasan

A Novel, Automatic Quality Control Scheme for Real Time Image Transmission

The first completely physical electro-thermal model is presented that is capable of
describing the large signal performance of MESFET- and HEMT-based, high power
microwave and millimeter wave monolithic and hybrid ICs, on timescales suitable for
CAD. The model includes the effects of self-heating and mutual thermal interaction
on active device performance with full treatment of all thermal non linearities. The
electrical description is provided by the rapid quasi-2D Leeds Physical Model and the
steady-state global thermal description is provided by a highly accurate and computationally
inexpensive analytical thermal resistance matrix approach. The order of
the global thermal resistance matrix describing 3-dimensional heat flow in complex
systems, is shown to be determined purely by the number of active device elements, not
the level of internal device structure. Thermal updates in the necessarily iterative, fully
coupled electro-thermal solution, therefore reduce to small matrix multiplications
implying orders of magnitude speed-up compared to the use of full numerical thermal
solutions capable of comparable levels of detail and accuracy.

W. Batty

A. J. Panks

R. G. Johnson

C. M. Snowden

Electro-thermal Modelling of Monolithic and Hybrid
Microwave and Millimeter Wave IC's

This work examines the complexity of scheduling for high level synthesis. It has been
shown that the problem of finding the minimum time schedule for a set of chains of
operations of two types using two processors, one of each type, is NP-complete.
However, for two chains only, a polynomial time algorithm can been obtained for
scheduling with two processors. The problem of scheduling a rooted binary tree of two
operation types on two processors, one of each type, has been shown to be NP-complete.
It has also been proved that absolute approximations for schedule length
minimization or processor minimization are NP-complete. A related resource
constrained scheduling problem has also been shown to be NP-hard.

C. A. Mandal

P. P. Chakrabarti

S. Ghose

Complexity of Scheduling in High Level Synthesis

Parag K. Lala

Guest Editorial

The use of a wavelet basis can lead to efficient methods for performing ab initio
electronic structure calculations of inherently localized structures. In this work wavelets
are used to construct an adaptive basis which is optimized dynamically throughout the
calculation. The computational effort of such a method should scale linearly with the
number of basis functions. The adaptive basis is tested for the case of bulk Si using only
a local s-pseudopotential.

D. A. Richie

P. von Allmen

K. Hess

Richard M. Martin

Electronic Structure Calculations Using
An Adaptive Wavelet Basis

The strain-dependence of electron transport in bulk Si and deep-submicron MOSFETsis investigated by full-band Monte Carlo simulation. On the bulk level, the drift velocityat medium field strengths is still enhanced above Ge-contents of 20&#37; in the substrate,where the low-field mobility is already saturated, while the saturation velocity remainsunchanged under strain. In an n-MOSFET with a metallurgical channel length of50nm, the saturation drain current is enhanced by up to 11&#37;, but this maximumimprovement is essentially already achieved at a Ge-content of 20&#37; emphasizing therole of the low-field mobility as a key indicator of device performance in the deep-submicronregime.

F. M. Bufler

P. D. Yoder

W.  Fichtner

Strain-Dependence of Electron Transport in BulkSi and Deep-Submicron MOSFETs

This paper introduces a new design approach that combines stages of logic and physical design. The logic function issynthesized and mapped to a two-dimensional array of logic cells. This array generalizes PLAs, XPLAs and cellular Maitracascades. Each cell can be programmed to a wire, an inverter, or a two-input AND, OR or EXOR gate (with any subset ofinputs negated). The gate can take any output of four neighbor cells and four neighbor buses as its inputs, and sends its resultback to them. This two-dimensional geometrical model is well suited for both fine-grain FPGA realization and sea-of-gatescustom ASIC layout. The comprehensive design method starts from a Boolean function, specified as SOP or ESOP, andproduces a rectangularly shaped structure of (mostly) locally connected cells. Two stages: restricted factorization, andcolumn folding, are discussed in more details to illustrate our general methodology.

Ning  Song

Marek A. Perkowski

Malgorzata  Chrzanowska-Jeske

Andisheh  Sarabi

A New Design Methodology for Two-DimensionalLogic Arrays

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VLSI Design