An effective logic synthesis procedure based on parallel and serial decomposition of a Boolean function is presented in thispaper. The decomposition, carried out as the very first step of the .synthesis process, is based on an original representationof the function by a set of r-partitions over the set of minterms. Two different decomposition strategies, namely serial andparallel, are exploited by striking a balance between the two ideas. The presented procedure can be applied to completelyor incompletely specified, single- or multiple-output functions and is suitable for different types of FPGAs includingXILINX, ACTEL and ALGOTRONIX devices. The results of the benchmark experiments presented in the paper show that,in several cases, our method produces circuits of significantly reduced complexity compared to the solutions reported in the literature.

Tadeusz  &#321;uba

Henry   Selvaraj

A General Approach to Boolean FunctionDecomposition and its Application in FPGABasedSynthesis

We propose a timing optimization technique for a complex finite state machine that consists of not only random logic but also data operators. In such a design, the timing critical path often forms a cycle and thus cannot be cut down easily by popular techniques such as pipelining or retiming. The proposed technique, based on the concept of <em>catalyst</em>, adds a functionally redundant block&#8212;which includes a piece of combinational logic and several other registers&#8212;to the circuits under consideration so that the timing critical paths are divided into stages. During this transformation, the circuit&#39;s functionality is not affected, while the speed is improved significantly. This technique has been successfully applied to an industrial application&#8212;a Built-In Self-Test (BIST) circuit for static random access memories (SRAMs). The synthesis result indicates a 47&#37; clock cycle time reduction.

Shi-Yu  Huang

Improving the Timing of Extended Finite State Machines Via Catalyst

Current mobile phone applications demand high performance from the DSP, and future
generations are likely to require even greater throughput. However, it is important to
balance these processing demands against the requirement of low power consumption
for extended battery lifetime. A novel low-power digital signal processor (DSP)
architecture CADRE (Configurable Asynchronous DSP for Reduced Energy) addresses
these requirements through a multi-level power reduction strategy. A parallel architecture
and configurable compressed instruction set meets the throughput requirements
without excessive program memory bandwidth, while a large register file reduces the
cost of data accesses. Sign-magnitude representation is used for data, to reduce switching
activity within the datapath. Asynchronous design gives fine-grained activity control
without the complexities of clock gating, and gives low electromagnetic interference.
Finally, the operational model of the target application allows for a reduced interrupt
structure, simplifying processor design by avoiding the need for exact exceptions.

Mike Lewis

Linda Brackenbury

CADRE: A Low-power, Low-EMI DSP Architecture for Digital Mobile Phones

This paper presents a numerical study of single-electron resonant tunnelling (RT) assisted bya few ionised donors in a laterally-confined resonant tunnelling diode (LCRTD). The 3Dmulti-mode S-matrix simulation is performed newly introducing the scattering potential ofdiscrete impurities. With a few ionised donors being placed, the calculated energy-dependenceof the total transmission rate shows new resonances which are donor-configurationdependent. Visualised electron probability density reveals that these resonances originate inRT via single-donor-induced localised states. The I-V characteristics show current steps oforder 0.1 nA per donor before the main current peak, which is quantitatively in good agreementwith the experimental results.

Hiroshi  Mizuta

Three-Dimensional S-Matrix Simulation ofSingle-Electron Resonant Tunnelling Through RandomIonised Donor States

We perform a rigorous comparison between the Spherical Harmonic (SH) and MonteCarlo (MC) methods of solving the Boltzmann Transport Equation (BTE), on a 0.05 &#956;mbase BJT. We find the SH and the MC methods give very similar results for the energydistribution function, using an analytical band-structure, at all points within the testeddevices. However, the SH method can be as much as seven thousand times faster than theMC approach for solving an identical problem. We explain the agreement by asymptoticanalysis of the system of equations generated by the SH expansion of the BTE.

C.-H.  Chang

C.-K.  Lin

N.  Goldsman

I. D. Mayergoyz

Spherical Harmonic Modeling of a 0.05 &#956;mBase BJT: A Comparison with Monte Carloand Asymptotic Analysis

Carl L. Gardner

Guest Editorial

The behavior of basic CMOS combinational gates in the presence of a floating gate defect is
characterized in order to investigate its detectability by <mml:math id="E1" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>I</mml:mi><mml:mrow><mml:mi>D</mml:mi><mml:mi>D</mml:mi><mml:mi>Q</mml:mi></mml:mrow></mml:msub></mml:mrow></mml:math>
. The defect is modeled at the
circuit level by the poly-bulk and metal-poly capacitances, which determine the quiescent
power supply current consumption (<mml:math id="E2" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>I</mml:mi><mml:mrow><mml:mi>D</mml:mi><mml:mi>D</mml:mi><mml:mi>Q</mml:mi></mml:mrow></mml:msub></mml:mrow></mml:math>
) of the defective circuit. The testing implications
on the type of defective gate are studied. Experimental measures have been made on basic
CMOS combinational modules designed with intentional floating gate defects. A good agreement
is observed between the simulation results and the experimental data. A conventional
ATPG for stuck-at faults is used to obtain the required exciting vector to test the floating gate
defects by <mml:math id="E3" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>I</mml:mi><mml:mrow><mml:mi>D</mml:mi><mml:mi>D</mml:mi><mml:mi>Q</mml:mi></mml:mrow></mml:msub></mml:mrow></mml:math>
 Testing.

Victor H. Champac

Joan Figueras

Current Testing of CMOS Combinational Circuits with
Single Floating Gate Defects

Smooth quantum hydrodynamic (QHD) model simulations of the resonant tunnelingdiode are presented which exhibit enhanced negative differential resistance (NDR) whencompared to simulations using the original <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>O</mml:mi><mml:mrow><mml:mo>(</mml:mo><mml:mrow><mml:msup><mml:mi>&#x210F;</mml:mi><mml:mn>2</mml:mn></mml:msup></mml:mrow><mml:mo>)</mml:mo></mml:mrow></mml:math> QHD model. At both 300 K and 77 K,the smooth QHD simulations predict significant NDR even when the original QHDmodel simulations predict no NDR.

Christian  Ringhofer

Smooth Quantum Hydrodynamic Model Simulationof the Resonant Tunneling Diode

Pradip K. Srimani

Guest Editor&#39;s Introduction

This paper presents a new VLSI architecture of the Motion Estimation in MPEG-2. Previously, a number of full search block matching algorithms (BMA) and architectures using systolic array have been proposed for motion estimation. However, the architectures have an inefficiently large number of external memory accesses. Recently, to reduce the number of accesses in one search block, a block matching method within a search area to reuse the search data is provided using systolic process arrays. To further reduce the data access and computation time during the block matching, we propose a new approach through the reuse of the previously-search data in two dimensions. Our new architecture in this paper is an extension from our previous work such that we reuse the previously-searches area not only between two consecutive columns but also between two consecutive rows, so as to entirely remove redundant memory accesses. Experimental results show that our architecture of increased area by 81&#37; can reduce 98&#37; of memory accesses. Total power reduction is 86&#37; in power estimation by SPICE model.

Bo-Sung  Kim

Jun-Dong  Cho

Maximizing Memory Data Reuse for Lower Power Motion Estimation

During the last decade, many different approaches have been proposed to solve the multiple-level synthesis problem withdifferent minimum functionally complete systems of primitive logic blocks. The most popular of them is the division-basedapproach. However, modem microelectronic technology provides a large variety of building blocks which considerablydiffer from those typically considered. The traditional methods are therefore not suitable for synthesis with many modembuilding blocks. Furthermore, they often fail to find global optima for complex designs and leave unconsidered someimportant design aspects. Some of their weaknesses can be eliminated without leaving the paradigm they are based on, otherones are more fundamental. A paradigm which enables efficient exploitation of the opportunities created by themicroelectronic technology is the general decomposition paradigm. The aim of this paper is to analyze and compare thegeneral decomposition approach and the division-based approach. The most important advantages of the generaldecomposition approach are its generality (any network of any building blocks can be considered) and totality (all importantdesign aspects can be considered) as well as handling the incompletely specified functions in a natural way. In many cases,the general decomposition approach gives much better results than the traditional approaches.

Frank   Volf

Lech  J&#243;&#378;wiak

Mario  Stevens

Division-Based Versus General Decomposition-Based Multiple-Level Logic Synthesis

A quantum beam of conserved particles is described as a Stationary Incoherent
Superposition of Wave packets (SISOW). Mean values of a SISOW are time-independent
confirming that the SISOW describes a stationary flux of particles. The SISOW
is a general entity that contains the Hamiltonian eigenstates as a particular limit.
The decomposition of the SISOW into wave packets provides intrinsic dynamic information
which is not accessible from Hamiltonian eigenstates. Within the SISOW
approach an exhaustive framework can be developed to be able to study dynamic
phenomena in quantum electronic devices such us current fluctuations, relaxation and
transient phenomena.

Xavier Oriols

Jordi Suñé

Study of Electronic Transport in Tunneling
Devices Using an Incoherent Superposition
of Time Dependent Wave Packets

A new switch-level fault simulation method for MOS circuits is presented that combines compiled switch-level simulation techniques and functional fault modeling of transistor faults with the new fault simulation algorithm of differential fault simulation. The fault simulator models both node stuck-at-0, stuck-at-1 faults and transistor stuck-on, stuck-open faults. Prior to simulation, the switch-level circuit components are compiled into functional models. The effect of transistor faults on the function of the circuit components is modeled by functional fault models that execute very fast during simulation. Every compiled circuit component is assigned a dominance attribute, which abstracts relative strength information in the circuit. Dominance is used during simulation to resolve the X-state due to fighting pull-up and pull-down transistor paths and also to deduce transistor fault detectability and fault equivalencies prior to simulation. The differential fault simulation algorithm developed for gate-level circuits is adapted for use at the switch-level. Differential fault simulation provides excellent performance with minimum memory requirements, although it incurs a higher overhead at the switch-level than at the gate-level due to the dynamic memory properties of MOS circuits.

Evstratios  Vandris

Gerald  Sobelman

Switch-level Differential Fault Simulation of MOS VLSI Circuits

Current drawn by a static CMOS VLSI integrated circuit during quiescent periods is extremely small and isnormally of the order of nanoamperes. However, it is remarkably susceptible to a number of failure modes. Manyfaults present in such ICs cause the quiescent power-supply current (IDDQ) to increase by several orders ofmagnitude. Some of these faults may not manifest themselves as logical faults, and would not be detected bytraditional IC test techniques.In large ICs, it may be hard to distinguish between larger IDDQ due to defects and elevated IDDQ due tonormal parameter variations. A statistical characterization of the problem is presented. This can be used todetermine the optimal size of partitions. A new information compression scheme is presented which can significantlyenhance resolution.

Yashwant K. Malaiya

Anura P. Jayasumana

Carol Q. Tong

Sankaran M. Menon

Resolution Enhancement in I<sub>DDQ</sub> Testingfor Large ICs

Dynamic reconfigurable field-programmable logic arrays (FPGAs) are receiving notableattention because of their much shorter reconfiguration time as compared withtraditional FPGAs. The short reconfiguration time is vital to applications such asreconfigurable computing and emulation. We show in this paper that testing anddiagnosis of the FPGA also can take advantage of its dynamic reconfigurability. Wefirst propose an efficient methodology for testing the interconnects of the FPGA, thenpresent several universal test and diagnosis approaches which cover all functional unitsof the FPGA. Experimental results show that our approach significantly reduces thetesting time, without additional cost for diagnosis.

Chi-Feng  Wu

Cheng-Wen  Wu

Testing and Diagnosing Dynamic Reconfigurable FPGA

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