Design for testability (DFT) techniques reduce testing costs at the price of extra hardware. Among the manyDFT techniques that have been proposed for this task are full scan, partial scan and hardware reset. In this paperwe explore a relatively new DFT method, called partial reset. Reset lines are added to only a subset of the flip-flopsand obtain reasonably high coverage. This approach has lower overhead in terms of test application timeand hardware area when compared to previous ones. Further enhancement of the controllability is obtained byusing multiple reset lines. The configuration of these multiple reset lines is described. This technique has beenevaluated on the 1989 ISCAS sequential benchmark circuits and obtained favorable results.

Ben  Mathew

Daniel G. Saab

Partial Reset: An Alternative DFT Approach

A high-speed 4-bit ALU has been designed for 1 V operation to demonstrate the usefulness of the back-gate forward substrate bias (BGFSB) method in 1.2 &#956;m N-well CMOS technology. The 4-bit ALU employs a ripple carry adder and is capable of performing eight operations - four arithmetic and four logical operations. The BGFSB voltage has been limited to <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mrow><mml:mo>|</mml:mo><mml:mrow><mml:mn>0.4</mml:mn></mml:mrow><mml:mo>|</mml:mo></mml:mrow></mml:mrow></mml:math> V. Delay time measurements are taken for all operations from the SPICE simulations with and without the back-gate forward substrate bias. A speed advantage of a factor of about 2&#8211;2.5 is obtained with BGFSB over the conventional design.

A.  Srivastava

D.  Govindarajan

A Fast ALU Design in CMOS for Low Voltage Operation

We present a VLSI synthesis environment dedicated to the design of image processing architectures. The environment includes a &#x201c;front-end&#x201d; data-flow emulator for validation of the algorithms and the RTL-synthesis system called ALPHA. The latter implements a stochastic search in the design space and produces efficient solutions considering the &#x201c;restricted&#x201d; domain of concerned applications. Two simulated Annealing (SA) algorithms run in sequence for data-path synthesis (scheduling and module selection) and then for control synthesis and data-path completion (binding). An interesting feature of the first optimization is the use of the data-flow graph regularity to predict the control influence in terms of the future design. A few designs have already been compiled under this environment including a default detector presented here.

Fran&#xe7;ois S. Verdier

Bertrand Zavidovique

A High Level Synthesis System for VLSI Image Processing Applications

A high speed 64b/32b integer divider employing digit-recurrence division method andthe on-the-fly conversion algorithm, wherein a fast normalizer is included, which is usedas the pre-processor of the proposed integer divider. For the sake of enhancingthroughput rate, the proposed divider uses a mixed radix-8/4/2 division instead of thetraditional radix-2 division. On-the-fly remainder adjustment is also realized in theconverter module of the divider. The entire design is written in Verilog HDL (hardwaredescription language) employing COMPASS 0.6 &#956;m 1P3M cell library (V3.0), and thensynthesized by SYNOPSYS. The simulation results indicate that our design is a betteroption than the existing long divider designs.

Chua-Chin  Wang

Chenn-Jung  Huang

I-Yen  Chang

Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library

Strategies for the design of ultra low power multipliers and multiplier-accumulators
are reported. These are optimized for asynchronous applications being able to take
advantage of data-dependent computation times. Nevertheless, the low power
consumption can be obtained in both synchronous and asynchronous environments.
Central to the energy efficiency is a dynamic-logic technique termed Conditional
Evaluation which is able to exploit redundancies within the carry-save array and deliver
energy consumption which is also heavily data-dependent.Energy efficient adaptations for handling two's complement operands are introduced.
Area overheads of the proposed designs are estimated and transistor level simulation
results of signed and unsigned multipliers as well as a signed multiplier-accumulator are given.Normalized comparisons with other designs show our approach to use less energy
than other published multipliers.

V. A. Bartlett

E. Grass

Exploiting Data-dependencies in Ultra Low-power DSP Arithmetic

Balance equations based on the moment method for the transport of electrons in silicon
semiconductors are presented. The energy band is assumed to be described by the Kane
dispersion relation. The closure relations have been obtained by employing the maximum
entropy principle.The validity of the constitutive equations for fluxes and production terms of the
balance equations has been checked with a comparison to detailed Monte Carlo
simulations in the case of bulk silicon.

A. M. Anile

O. Muscato

V. Romano

Moment Equations with Maximum Entropy Closure
for Carrier Transport in Semiconductor Devices:
Validation in Bulk Silicon

On-the-fly calculations of area and performance are a typical part of the computer-aided iterative design processin VLSI, which aims at a satisfactory tradeoff of various conflicting objectives, among which are test-generationtime and test-set size. However, determining test sets on-the-fly as one circuit is transformed into another isextremely difficult. Our goal is to add a test dimension to the design optimization process that complementsmethods concerned with area and performance optimization. We define a set of logic transformations that resultin easily computed changes to test sets. Test-set preserving (TSP) transformations preserve a combinational circuit’stest sets, while test-set altering (TSA) transformations introduce a minimum number of tests needed to maintaincompleteness. We illustrate our approach with a family of adders that share area-efficient tree structures anddiffer in the amount of carry-lookahead used to accelerate carry computation. Members include the ripple-carryadder, which has no lookahead, and the standard carry-lookahead adder, which exploits lookahead across allinputs. It is straightforward to derive area and performance measures for this class of adders. Given an n-bitadder with lookahead degree k, we determine a sequence of circuit transformations that produce the adder ofdegree k2 and test sets of minimum size. Optimal test sets of size k(logkn + 1) + 2 result for arbitrary n and k,which improve significantly upon previously reported tests.

Michael J. Batek

John P. Hayes

Optimal Testing and Design of Adders

The effects of Built-In Current Sensors (BICS) on <mml:math id="E1" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>I</mml:mi><mml:mrow><mml:mi>D</mml:mi><mml:mi>D</mml:mi><mml:mi>Q</mml:mi></mml:mrow></mml:msub></mml:mrow></mml:math>
 measurements as well as on the
performance of the circuit under test are considered. Most of the Built-In Current Sensor
designs transform the ground terminal of the circuit under test into a virtual ground. This
causes increases in both propagation delay and <mml:math id="E2" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>I</mml:mi><mml:mrow><mml:mi>D</mml:mi><mml:mi>D</mml:mi><mml:mi>Q</mml:mi></mml:mrow></mml:msub></mml:mrow></mml:math>
 sampling time with the increase in the
number of gates, affecting both test as well as operational performance. The effects that
current sensors have on the operational and test performance of a circuit are considered.
Circuit partitioning may be used for overcoming the effects of BICS on <mml:math id="E3" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>I</mml:mi><mml:mrow><mml:mi>D</mml:mi><mml:mi>D</mml:mi><mml:mi>Q</mml:mi></mml:mrow></mml:msub></mml:mrow></mml:math>
 measurements
as well as on the performance of the circuit under test.

Sankaran M. Menon

Yashwant K. Malaiya

Anura P. Jayasumana

Carol Q. Tong

Operational and Test Performance in the Presence of
Built-in Current Sensors

Bipolar Emitter Coupled Logic (ECL) devices can now be fabricated at higher densities and consumes much lower power. Behaviour of simple and complex ECL gates are examined in the presence of physical faults. The effectiveness of the classical stuck-at model in representing physical failures in ECL gates is examined. It is shown that the conventional stuck-at fault model cannot represent a majority of circuit level faults. A new augmented stuck-at fault model is presented which provides a significantly higher coverage of physical failures. The model may be applicable to other logic families that use logic gates with both true and complementary outputs. A design for testability approach is suggested for on-line detection of certain error conditions occurring in gates with true and complementary outputs which is a normal implementation for ECL devices.

Fault Modeling of ECL for High Fault Coverage of Physical Defects

We present a numerical simulation of the operation of a chain of 3 Quantum Cellular
Automanton (QCA) cells, with the inclusion of a realistic procedure to enforce, with an
externally applied bias voltage unbalance, the polarization of the first cell. The
polarization state is shown to propagate correctly, as long as the bias unbalance applied
to the electrodes of the first cell is not so large as to directly perturb nearby cells. The
addition of dummy cells is needed to balance the asymmetries existing at the ends of a
chain: this is an indication of further difficulties, that may become relevant if fabrication
of more complex arrays is attempted.

M. Girlanda

M. Macucci

Simulation of a Complete Chain of QCA Cells
with Realistic Potentials

In this paper, we perform a mathematical study of a semiconductor superlattice. Since thethickness of the layers is very small, quantization plays an important role. The modellingis therefore given by a Schr&#246;dinger equation with a periodic potential. The scaled latticethickness is denoted by a small parameter &#8455; which is of the same order of magnitude asthe Planck constant. When this parameter tends to zero, i.e., the semi-classical limit, weobtain classical transport of the charge carriers described by a Vlasov equation.

Philippe  Bechouche

Semi-classical Limit in a Semiconductor Superlattice

A general framework for designing current-mode CMOS analog multiplier/divider
circuits based on the cascade connection of a geometric-mean circuit and a squarer/divider is presented. It is shown how both building blocks can be readily obtained from
a generic second-order MOS translinear loop. Various implementations are proposed,
featuring simplicity, favorable precision and wide dynamic range. They can be successfully
employed in a wide range of analog VLSI processing tasks. Experimental
results of two versions, based on stacked and folded MOS-translinear loops and fabricated
in a 2.4-μm CMOS process, are provided in order to verify the correctness of
the proposed approach.

Antonio J. Lopez-Martin

Alfonso Carlosena

Design of MOS-translinear Multiplier/Dividers in Analog VLSI

Carl L. Gardner

Guest Editorial

A new algorithm for the identification of disjoint bi-decomposition in Boolean functions from its Walsh spectrum is proposed. The type of bi-decomposition and its existence is derived from the knowledge of a subset of Walsh spectrum for a Boolean function. All three types of bi-decomposition are considered including OR, AND and EXOR type. A filtering procedure that uses just few Walsh spectral coefficients (SC) is applied to quickly eliminate the functions that are not bi-decomposable and hence the algorithm is very efficient. The type of bi-decomposition and affirmation/negation of variables in its logic sub-functions are directly identified by manipulation on the reduced cubical representation of Boolean functions and their corresponding Walsh spectra. The presented algorithm has been implemented in C and tested on the standard benchmark functions. The number of Boolean functions having various disjoint bi-decompositions has also been enumerated.

Bogdan J. Falkowski

Sudha  Kannurao

Identification of Disjoint Bi-decompositions in Boolean Functions through Walsh Spectrum

We present the design for the two VLSI components used in a processor-to-memory interconnection network fora shared memory system. These components allow the combining of requests that are destined to the same memorylocation. The design contains both semi-systolic queues and an associative &#8220;wait buffer.&#8221; Transition equations andschematics of the critical pieces of the design are included.

Susan R. Dickey

Richard  Kenner

Design of Components for a Low Cost CombiningSwitch

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