A semicustom ASIC design methodology is used to develop a low power DSP core formobile (battery powered) applications. Different low power design techniques are used,including dual voltage, low power library elements, accurate power reporting, pseudomicrocode,transition-once logic, clock gating, and others.

Alvar  Dean

David  Garrett

Mircea R. Stan

Sebastian  Ventrone

Low Power Design for ASIC Cores

Carl L. Gardner

Guest Editorial

Efficient, generalized delay and power equations are proposed for large scale CMOS circuit analysis and optimization achieved by transistor and interconnect wire minimization. The proposed model equations are used to analyze the entire power-delay trade-off with less complexity and faster computation time. New equations can be adopted to perform the optimization of transistor and interconnect wire size concurrently. A single stage CMOS circuit and a clock generation block fabricated in 0.48 um CMOS process are given as experimental examples.

Sangho  Lee

Edwin W. Greeneich

CMOS Delay and Power Model Equations for Simultaneous Transistor and Interconnect Wire Analysis and Optimization

A lookup table based method to minimize Generalized Partially-Mixed-Polarity Reed-Muller (GPMPRM) expansions with k mixed polarity variables has been developed.The new algorithm can produce solutions based on the desired cost criteria for thesystems of completely specified functions.

Bogdan J. Falkowski

Chip-Hong  Chang

Minimization of k-Variable-Mixed-Polarity Reed-Muller Expansions

We outline a systematic nonperturbative derivation of a hierarchy of closed systems of
moment equations that can be applied to any kinetic description of electrons in a semiconductor.
This entropy based closure procedure extends one that was introduced in the context of
gas dynamics. In the context of semiconductors, this procedure yields generalizations of socalled
hydrodynamic models. It is illustrated on the semiclassical Boltzmann-Poisson equation
for a single conduction band in the parabolic band approximation.

C. David Levermore

Moment Closure Hierarchies for the Boltzmann-Poisson Equation

We propose a logic synthesis system that includes power optimization after technology
mapping. Our approach is unique in that our post-mapping logic transformations take
into account information on circuit delay, capacitance, arrival times, glitches, etc., to
provide much better accuracy than previously proposed technology-independent power
optimization methods. By changing connections in a mapped circuit, we achieve power
improvements up to 13% in case of area- or delay-optimized circuits, with reductions
also in area and delay. We show that by applying the proposed technique on circuits
that are already restructured for lower switching activity using the technique presented
in [11], total power savings up to 59% in case of area-optimized circuits and 38% in case
of delay-optimized circuits are achievable. The post-mapping transformations are based
on the transition density model of circuit switching activity and the concept of
permissible logic functions. The techniques presented here are applicable equally well to
both synchronous and asynchronous circuits. The power measurements are done under
a general delay model.

Rajendran Panda

Farid N. Najm

Post-Mapping Transformations for Low-Power Synthesis

Here we present a new method for the decomposition of a Finite State Machine (FSM) into a network of interacting FSMsand a framework for the functional verification of the FSM network at different levels of abstraction. The problem ofdecomposition is solved by output partitioning and state space decomposition using a multiway graph partitioningtechnique. The number of submachines is determined dynamically during the partitioning process. The verificationalgorithm can be used to verify (a) the result of FSM decomposition on a behavioral level, (b) the encoded FSM network,and (c) the FSM network after logic optimization. Our verification technique is based on an efficient enumeration-simulationmethod which involves traversal of the state transition graph of the prototype machine and simulation of the decomposedmachine network. Both the decomposition and verification/simulation algorithms have been implemented as part of aninteractive FSM synthesis system and tested on a set of benchmark examples.

Zafar   Hasan

Maciej J. Ciesielski

FSM Decomposition and Functional Verification ofFSM Networks

The logic behavior and performance of ECL gates under a set of defect models are examined. These are comparedwith equivalent set of BiCMOS and CMOS gates. It is found that logical fault testing is inadequate for obtaininga sufficiently high fault coverage, e.g., 79&#37; for ECL versus 54&#37; for BiCMOS and 69&#37; for CMOS equivalentgates. Performance degradation faults such as delay, current and Voltage Transfer Characteristics (VTC) or NoiseMargin (NM) faults are analyzed as applied to these gates. It is shown that logical fault testing with delay faulttesting yields the highest fault coverage for BiCMOS and CMOS gates (around 95&#37;). However, for equivalentECL gates to attain a fault coverage of around 98&#37;, both logical and NM fault testing have to be used.

M. O. Esonu

D.  Al-Khalili

C.  Rozon

Fault Characterization and Testability Analysis ofEmitter Coupled Logic and Comparison with CMOS&#38; BiCMOS Circuits

Neighboring line switching can contribute to a large portion of the delay of a line for today's deep submicron designs. The impact of this switching on delay is usually estimated by scaling the coupling capacitances (often by a factor of 2) and modeling them as grounded. This simple approach has been shown to be overly pessimistic in some cases, while somewhat optimistic in others. Apart from the delay modeling inaccuracies, the temporal and functional isolation of the aggressors can contribute to the pessimism. This paper introduces TACO, a timing analysis approach that addresses both these issues. TACO captures the provably worst-and best-case delays as a function of the timing-window inputs to the gates. We then present a comprehensive ATPG-based approach that uses functional information to identify valid interactions between coupled lines. Our algorithm accounts for glitches on aggressors that can be caused by static and dynamic hazards in the circuit. Results on industrial examples and benchmark circuits show the value of our approach.

Ravishankar  Arunachalam

Ronald DeShawn Blanton

Lawrence T. Pileggi

Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation

As the demand for higher performance computers for the processing of remote sensingscience algorithms increases, the need to investigate new computing paradigms isjustified. Field Programmable Gate Arrays enable the implementation of algorithmsat the hardware gate level, leading to orders of magnitude performance increase overmicroprocessor based systems. The automatic classification of spaceborne multispectralimages is an example of a computation intensive application that can benefitfrom implementation on an FPGA-based custom computing machine (adaptive orreconfigurable computer). A probabilistic neural network is used here to classify pixelsof a multispectral LANDSAT-2 image. The implementation described utilizes Javaclient/server application programs to access the adaptive computer from a remote site.Results verify that a remote hardware version of the algorithm (implemented on anadaptive computer) is significantly faster than a local software version of the samealgorithm (implemented on a typical general-purpose computer).

Marco A. Figueiredo

Clay S. Gloster

Mark  Stephens

Corey A. Graves

Mouna   Nakkar

Implementation of Multispectral Image Classificationon a Remote Adaptive Computer

Partitioning is a fundamental problem in the design of VLSI circuits. In recent years, themulti-level partitioning approach has been used with success by a number ofresearchers. This paper describes a new multi-level partitioning algorithm (PART) thatcombines a blend of iterative improvement and clustering, biasing of node gains, andlocal uphill climbs. PART is competitive with recent state-of-the-art partitioningalgorithms. PART was able to find new lower cuts for many benchmark circuits. Undersuitably mild assumptions, PART also runs in linear time.

Youssef  Saab

A New 2-way Multi-level Partitioning Algorithm

The use of associative memories&#8212;storage devices that allow data retrieval based on contents&#8212;has often beensuggested to speed up the performance of many applications. Until recently, using such content-addressablememories (CAMs) was unfeasible due to their high hardware cost. However, the advent of VLSI has made theclass of fully-parallel associative memory cost-effective for implementation. This paper briefly overviews designof several fully parallel associative memories proposed in the literature, concentrating on the design of fully-parallel&#952;-search CAMs.Existing market realities require that product development be fast and predictable. As a result, design flexibilityand automation are becoming increasingly important design features. Using the various CAM designs reviewed,the paper collects the features of these designs into a general, modular CAM organization and describes its majorcomponents. The modular CAM organization can be used to design application specific CAMs of varying degreesof functionality. Design and space complexity of a sample associative memory suitable for relational databaseoperations is studied. Finally, the application of genetic algorithms as a means to developing automated designtools for fabrication of modular VLSI design chips is discussed.Given a library of CAM modules, the desired functionality and a set of speed and area constraints, thisoptimization technique produces a suitable CAM design. The proposed technique has been implemented and itsperformance measure is briefly addressed.

A. R. Hurson

S.  Pakzad

Modular Scheme for Designing Special PurposeAssociative Memories and Beyond

We introduce, in this paper, Clustered Time Warp (CTW), an algorithm for the parallelsimulation of discrete event models on a general purpose distributed memoryarchitecture. CTW has its roots in the problem of distributed logic simulation. It is ahybrid algorithm which makes use of Time Warp between clusters of LPs and asequential algorithm within the clusters whereas Time Warp is traditionallyimplemented between individual LPs.We also develop a family of three checkpointing algorithms for use with CTW, each ofwhich occupies a different point in the spectrum of possible trade-offs between memoryusage and execution time. The algorithms were implemented and tested on several digitallogic circuits and their speed, number of states saved and maximal memory consumptionwere compared to Time Warp. Our results showed that one of the algorithms saved anaverage of 40&#37; of the maximal memory consumed by Time Warp while the other twodecreased the maximal usage by 15 and 22&#37;, respectively. The latter two algorithmsexhibited a speed comparable to Time Warp, while the first algorithm was 60&#37; slower.We investigated the scalability of CTW using 3 different queuing models and differentservice-time distributions and showed that the algorithm acts to limit the explosion ofrollbacks exhibited by Time Warp. Furthermore, we showed that the memoryrequirements for CTW are three times smaller than that of Time Warp for one modeland half as large for the two other models.

Herv&#233;  Avril

Carl  Tropper

Scalable Clustered Time Warp and Logic Simulation

We describe a theoretical methodology for screening potential gate dielectric materials.A recently proposed method for constructing realistic structural models of the Si-dielectricinterface is used to generate the Si-SiO2-Si and Si-SiON-SiO2-Si model metal-oxide-semiconductor (MOS) structures. We discuss methods to estimate the valenceband discontinuity at the corresponding interface. We use Landauer&#39;s ballistic transportapproach to investigate the low bias leakage through these ultrathin dielectric layers.

Alexander A. Demkov

Xiaodong  Zhang

Heather  Loechelt

Theoretical Investigation of UltrathinGate Dielectrics

In this paper, we present two studies. The first study constitutes an assessment of the effectiveness
of IDDQ (quiescent power supply current) in detecting transistor-level defects for
three CMOS logic design styles. This study was carded out by designing, simulating, fabricating,
and testing CMOS devices with built-in defects. The second study involves an
assessment of IDDQ in a production-type environment and the effect of bum-in on IDDQ
levels. This study was carried out in a production facility. The results show that IDDQ testing
can detect some types of defects in precharge and pseudo-NMOS circuits but may require
partitioning circuitry for the latter.

A. Toukmaji

R. Helms

R. Makki

W. Mikhail

R. Toole

IDDQ Testing Experiments for Various CMOS Logic
Design Structures

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VLSI Design