VLSI Design

Delay Time Estimation Model for Large Digital CMOS Circuits

A Combined Coefficient Segmentation and Block Processing Algorithm for Low Power Implementation of FIR Digital Filters

Automatic FSM Synthesis for Low-power Mixed Synchronous/Asynchronous Implementation

Abstract Architecture Representation Using VSPEC

Theory and Modeling of Lasing Modes in Vertical Cavity Surface Emitting Lasers

SENECA: a New Program for the Analysis of Single-Electron Devices

Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors

A Generalized Finite Element Method for Hydrodynamic Modeling of Short-channel Devices

An Integrated Hardware Array for Very High Speed Logic Simulation

COPAS: A New Algorithm for the Partial Input Encoding Problem

Realistic Fault Modeling and Extraction of Multiple Bridging and Break Faults

On the Structure and Closure-Condition of the Hydrodynamic Model

On the Minimum Density Interconnection Tree Problem

Configurable 2-D Linear Feedback Shift Registers for VLSI Built-in Self-test Designs

An ILP Formulation for Minimizing the Number of Feedthrough Cells in a Standard Cell Placement

VLSI Design

Table of Contents

Table of Contents

Delay Time Estimation Model for Large Digital CMOS Circuits

A Combined Coefficient Segmentation and Block Processing Algorithm for Low Power Implementation of FIR Digital Filters

Automatic FSM Synthesis for Low-power Mixed Synchronous/Asynchronous Implementation

Abstract Architecture Representation Using VSPEC

Theory and Modeling of Lasing Modes in Vertical Cavity Surface Emitting Lasers

SENECA: a New Program for the Analysis of Single-Electron Devices

Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors

A Generalized Finite Element Method for Hydrodynamic Modeling of Short-channel Devices

An Integrated Hardware Array for Very High Speed Logic Simulation

COPAS: A New Algorithm for the Partial Input Encoding Problem

Realistic Fault Modeling and Extraction of Multiple Bridging and Break Faults

On the Structure and Closure-Condition of the Hydrodynamic Model

On the Minimum Density Interconnection Tree Problem

Configurable 2-D Linear Feedback Shift Registers for VLSI Built-in Self-test Designs

An ILP Formulation for Minimizing the Number of Feedthrough Cells in a Standard Cell Placement