A recent paper by Bailey [1] contains a theorem stating that the idealized execution times of unit-delay, synchronous and conservative asynchronous simulations are equal under the conditions that unlimited number of processors are available and the evaluation time of each logic element is equal. Further it is shown that the above conditions result in a lower bound on the execution times of both synchronous and conservative asynchronous simulations. Bailey's above important conclusions are derived under a strict assumption that the inputs to
a circuit remain fixed during the entire simulation. We remove this limitation and, by extending the analyses to multi-input, multi-output circuits with an arbitrary number of input events, show that the conservative asynchronous simulation extracts more parallelism and executes faster than synchronous simulation in general. Our conclusions are supported by a comparison of the idealized execution times of synchronous and conservative asynchronous algorithms on ISCAS combinational and sequential benchmark circuits.

Ausif Mahmood

William I. Baker

An Evaluation of Parallel Synchronous and Conservative Asynchronous Logic-Level Simulations

An important class of biological molecules-proteins called ionic channels&#8211;conductions (like Na+, K+, Cl-) through a narrow tunnel of fixed charge (&#8216;doping&#8217;). Ionic channels are the main pathway by which substances move into cells and so are of greatbiological and medical importance: a substantial fraction of all drugs used by physicians act on channels. Channels can be studied in the tradition of computational electronics. Drift diffusion equations form an adequate model of IV relations of 6 different channel proteins in &#820; 10 solutions over &#177;150 mV. Ionic channels can also be studied with thepowerful techniques of molecular biology. Atoms can be modified one at a time and the location of every atom can be determined. Ionic channels are natural nanotubes that can be controlled more precisely and easily than physical nanostructures but biologists need help if realistic simulations are to be done atomic detail.

Bob  Eisenberg

Ionic Channels in Biological Membranes: NaturalNanotubes Described by the Drift-Diffusion Equations

Synthesis for testability ensures that the synthesized circuit is testable by exploring the fundamental relationship between don't care and redundancy. With the exploration of the relationship, redundancy removal can be applied to improve the testability, reduce the area and improve the speed of a synthesized circuit. The test generation problems have been adequately solved, therefore an innovative testability synthesis strategy is necessary for achieving the maximum fault coverage and area reduction for maximum speed. This paper presents a testability synthesis methodology applicable to a top–down design method based on the identification and removal of redundant faults. Emphasis has been placed on the testability synthesis of a high-speed binary jumping carry adder. A synthesized 32-bit testable adder implemented by a 1.2 μm CMOS technology performs addition in 4.09 ns. Comparing with the original synthesized circuit, redundancy removal yields a 100% testable design with a 15% improvement in speed and a 25% reduction in area.

Chien-In Henry Chen

Mahesh Wagh

Testability Synthesis for Jumping Carry Adders

A new method for implementing two-level logic circuits, which exhibit minimal power
dissipation, is introduced. Switching activity reduction of the logic network nodes is
achieved by adding extra input signals to specific gates. Employing the statistic properties
of the primary inputs, a new concept for grouping the input variables with similar
features is introduced. Appropriate input variables are chosen for reducing the
switching activity of a logic circuit. For that purpose, an efficient synthesis algorithm,
which generates the set of all groups of the variables and solves the minimum covering
problem for each group is developed. The comparison of the results, produced by the
proposed method, and those from ESPRESSO shows that a substantial power reduction
can be achieved.

G. Theodoridis

S. Theoharis

D. Soudris

C. Goutis

A New Method for Low Power Design of Two-Level Logic Circuits

Hydrodynamic or continuum descriptions of electron transport have long been used for modeling and simulating
semiconductor devices. In this paper, we use classical field theory ideas to discuss the physical foundations of such
descriptions as applied specifically to high-field transport regimes. The classical field theory development of these
types of models is of interest because it differs significantly from and may be viewed as complementary to
conventional derivations based on the Boltzmann equation: After outlining the general field theoretic principles
upon which our development of fluid-based high-field transport descriptions is based, we study several specific
models both analytically and using numerical simulation. These models provide an overall framework for
understanding and extending various theories which have appeared in the literature. Most importantly, they
emphasize the importance of including memory or history effects and viscosity in describing high-field transport.
In all of this our aim is a unified and synoptic view unencumbered with microscopic details. Obtaining quantitative
agreement with specific experiments and/or microscopic simulations is only of secondary importance. We share
the view that continuum approaches can provide succinct and computationally-efficient models needed for current
and future semiconductor device analysis and engineering. At the same time, we believe that these models need
not be phenomenological but can be given solid physical foundation in macroscopic principles.

M. G. Ancona

Hydrodynamic Models of Semiconductor
Electron Transport at High Fields

Recent scanning tunneling microscopy (STM) studies on the (111) faces of noble metals have
directly imaged electronic surface-confined states and dramatic standing-wave patterns have
been observed 1,2]. We solve for the local density of electronic states in these “leaky” quantum
corral confinement structures using a coherent elastic scattering theory. We seek solutions
of the two-dimensional Schrödinger equation compatible with non-reflecting boundary
conditions which asymptotically satisfy the Sommerfeld radiation condition [11,14]. The
large matrices generated by the discretization of realistic quantum corral structures require the
use of sparse matrix methods. In addition, a parallel finite element solution was undertaken
using the message passing interface standard (MPI) and the Portable, Extensible, Toolkit for
Scientific Computation (PETSc) [5] for an efficient computational solution on both distributed
and shared memory architectures. Our calculations reveal excellent agreement with the
reported experimental dl/dV STM data.

Henry K. Harbury

Wolfgang Porod

Parallel Computation for Electronic Waves in Quantum Corrals

This paper presents two primary results relevant to physical design problems in CAD/VLSI through a case study of the linear placement problem. First a local search mechanism which incorporates a sophisticated neighborhood operator based on constraint relaxation is proposed. The strategy exhibits many of the desirable features of analytical placement while retaining the flexibility and non-determinism of local search. The second and orthogonal contribution is in netlist clustering. We characterize local optima in the linear placement problem through a simple visualization tool&#8212;the displacement graph. This characterization reveals the relationship between clusters and local optima and motivates a dynamic clustering scheme designed specifically for escaping such local optima. Promising experimental results are reported.

Sung-Woo  Hur

John  Lillis

Relaxation and Clustering in a Local Search Framework: Application to Linear Placement

We present a framework for combining Voltage Scaling (VS) and Gate Sizing (GS)
techniques for power optimizations. We introduce a fast heuristic for choosing gates for
sizing and voltage scaling such that the total power is minimized under delay constraints.
We also use a more accurate estimate for determining the power dissipation of
the circuit by taking into account the short circuit power along with the dynamic power.
A better model of the short circuit power is used which takes into account the load
capacitance of the gates. Our results show that the combination of VS and GS perform
better than the techniques applied in isolation. An average power reduction of 73% is
obtained when decisions are taken assuming dynamic power only. In contrast, average
power reduction is 77% when decisons include the short circuit power dissipation.

Anshuman Nayak

Malay Haldar

Prith Banerjee

Chunhong Chen

Majid Sarrafzadeh

Power Optimization of Delay Constrained Circuits

Joseph W. Jerome

Classical and Quantum Hydrodynamic Device Models and Energy Transport

We have studied quantum transport in both Si and GaAs interband tunneling diodes(ITD&#39;s). In the simulation, a non-equilibrium Green&#39;s function method based anempirical tight binding theory has been used to take into account evanescent-wavematching at interfaces and realistic band structures. Comparison has been madebetween the results of our multiband (MB) model and those of conventional two-band(2B) model. As a result, it is found that the current&#8211;voltage (I&#8211;V) characteristics of theSi ITD have considerably smaller peak current density than the conventional 2B model,since our MB model reflects correctly the indirect gap band structure. On the otherhand, in the GaAs ITD, there is small difference between the two models, becausetunneling occurs between the conduction band and the valence band at F point. It isalso found that the matching of evanescent electron modes is essentially necessary toinclude the valley-mixing effects at the tunneling interfaces.

Matsuto  Ogawa

Ryuichiro  Tominaga

Tanroku  Miyoshi

Tight Binding Simulation of Quantum Transportin Interband Tunneling Devices

We have suggested a novel family of wireless single-electron digital devices, based on the
parametric excitation principle. The basic cell is a short array of small conducting islands separated
by tunnel barriers with relatively low capacitance and conductance. External rf (clock)
field creates conditions for spontaneous breaking of the charge symmetry of the cell. The
symmetry may be broken by the signal field provided by the neighboring cell(s). This mode
ensures robust operation of the parametron-based logic circuits. Moreover, these devices may
be reversible, dissipating energy well below kBT 1n2 per logic operation.

Konstantin K. Likharev

Alexander N. Korotkov

Single-Electron Parametron

Ausif  Mahmood

Hardware Accelerators for VLSI Design

Due to the significant contribution of interconnect to the area and speed of today's circuits
and the technological trend toward smaller and faster gates which will make the effects of
interconnect even more substantial, interconnect optimization must be performed during all
phases of the design. The premise of this paper is that by increasing the interaction between
logic synthesis and physical design, circuits with smaller area and interconnection length,
and improved performance and routability can be obtained compared to when the two processes
are done separately. In particular, this paper describes an integrated approach to
technology mapping and physical design which finds solutions in both domains of design
representation simultaneously and interactively. The two processes are performed in lockstep:
technology mapping takes advantage of detailed information about the interconnect
delays and the layout cost of various optimization alternatives; placement itself is guided by
the evolving logic structure and accurate path-based delay traces. Using these techniques,
circuits with smaller area and higher performance have been synthesized.

Massoud Pedram

Narasimha Bhat

Ernest S. Kuh

Combining Technology Mapping With Layout

Molecular wires have several promising features, that would appear to make them ideal
for advanced interconnects in nanoscale electronic devices. We discuss several aspects of
the linear and nonlinear conductance of molecular wire interconnects. Topics include
energy dependence of molecular conductance, resonant tunneling behavior, control of
conductance by molecular structure and geometry, length dependence including the
tunneling regime energetics. Design rules using molecular interconnects will differ
substantially from those with more standard, lithographically structured silicon
interconnects. In particular, the dissipation mechanisms will differ, both tunneling and
ballistic regimes should be available, coulomb blockade and staircase behavior will be
observed (but under differing conditions) and fabrication of gate electrodes is a challenge.

Mathieu Kemp

Vladimiro Mujica

Adrian Roitberg

Mark A. Ratner

Molecular Wire Interconnects: Chemical Structural Control, Resonant Tunneling and
Length Dependence

Rectangular dualisation is a technique used to generate rectangular topologies for use in top-down floorplanning
of integrated circuits. In order for this technique to be used in a floorplanning system, its input, the connectivity
graph representing an integrated circuit has to fulfill a number of conditions. This paper presents an efficient
algorithm that transforms an arbitrary connected graph, representing an integrated circuit, into another graph
that is guaranteed to fulfill these conditions and to admit rectangular duals. Effectively, the algorithm solves the
global routing problem by using three techniques: passthrough, wiring blocks and collapsed wiring blocks. Resulting
floorplans may be passed to a chip assembler and detailed router package to complete the layout. This paper also
introduces a novel technique to transform a tree of biconnected sub-graphs into a block neighbourhood graph
that is a path.

Marwan A. Jabri

Building Rectangular Floorplans–A Graph
Theoretical Approach

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VLSI Design