We present an effective solution to the linear placement problem, which has several applications in the physicaldesign of integrated circuits. Our approach belongs to the class of iterative improvement heuristics. The importantdifference of this new technique from the previous ones is in its moves, and in the order of application of thesemoves. A phase of the algorithm begins with simple moves and gradually shifts towards more complex moves.Phases are repeated as long as further improvement is possible. Our experimental results show that nearly optimalsolutions can be achieved. For a number of examples collected from the literature, our algorithm generatedoptimal solutions.

Youssef  Saab

Cheng-Hua  Chen

An Effective Solution to the LinearPlacement Problem

A digital circuit includes two main parts: a controller and a datapath. After connection of these two parts, both are subject to a sharp fall in testability due to the lack of controllability and observability at the interface. In this paper, we propose a method for specifying the control part in order to restore the testability of the datapath to a level close to the initial one, in other words its testability before connection. This testability driven specification affects the next state logic as well as the decoder part of the controller but does not make use of any scan-based element. Based on the finite automata theory and on results of a testability analysis performed on the datapath, the proposed method entails very little area penalty.

M. L. Flottes

B.  Rouzeyre

L.  Volpe

Improving Datapath Testability by Modifying Controller Specification

Fadi J. Kurdahi

Linking Behavioral, Structural, and Physical Modelsof Hardware

A set of software tools for the determination of the band structure of zinc-blende,
wurtzite, 4H, and 6H semiconductors is presented. A state of the art implementation of
the nonlocal empirical pseudopotential method has been coupled with a robust simplex
algorithm for the optimization of the adjustable parameters of the model potentials.
This computational core has been integrated with an array of Matlab functions, providing
interactive functionalities for defining the initial guess of the atomic pseudopotentials,
checking the convergence of the optimization process, plotting the resulting
band structure, and computing detailed information about any local minimum.
The results obtained for wurtzite-phase III-nitrides (ALN, GaN, InN) are presented as a
relevant case study.

Enrico Ghillino

Carlo Garetto

Michele Goano

Giovanni Ghione

Enrico Bellotti

Kevin F. Brennan

Simplex Algorithm for Band Structure Calculation
of Noncubic Symmetry Semiconductors:
Application to III-nitride Binaries and Alloys

This paper describes the design of an ASIC chip for thinning of graylevel images. The chip implements a Min-Max skeletonization algorithm and is based on a pipeline architecture where each stage of the pipeline performs masking operations on the graylevel images. The chip operates in real time at a frequency of 8 MHz and utilizes about 321 mils &#215; 410 mils of silicon area.

B.  Majumdar

V. V. Ramakrishna

P. S. Dey

A. K. Majumdar

Design of an ASIC Chip for Skeletonization of Graylevel Digital Images

A VLSI implementation of a dedicated digital signal processor is presented. Theprocessor is tailored for efficient implementation of transform domain adaptive filters. Itincorporates a butterfly processor which performs butterfly operation to implement therequired transformation. It is also able to perform complex addition, subtraction andmultiplication. The butterfly processor makes use of a redundant binary tree multiplierwith a recently proposed coding of signed-digit numbers which reduces the number oflevels in the tree by one. An on-chip read only memory holds the transformationcoefficients. The contents of the ROM determine the type of transform. The processorincorporates an ALU to perform integer arithmetic, address calculations andimplementation of circular memory scheme. For fastest accessibility, the essentialvariables of the algorithm are implemented in a register fire.

Ali  Najafi

Behrouz  Farhang-Boroujeny

Ganesh S. Samudra

A VLSI Design for Implementation of TransformDomain Adaptive Filters

Jun-Dong  Cho

Guest Editorial

Stephan  Olariu

Rong  Lin

Placement of multiple dies on an MCM or high-performance VLSI substrate is a nontrivialtask in which multiple criteria need to be considered simultaneously to obtain atrue multi-objective optimization. Unfortunately, the exact physical attributes of adesign are not known in the placement step until the entire design process is carried out.When the performance issues are considered, crosstalk noise constraints in the formof net separation and via constraint become important. In this paper, for betterperformance and wirability estimation during placement for MCMs, several performanceconstraints are taken into account simultaneously. A graph-based wirabilityestimation along with the Genetic placement optimization technique is proposed tominimize crosstalk, crossings, wirelength and the number of layers. Our work issignificant since it is the first attempt at bringing the crosstalk and other performanceissues into the placement domain.

Jun Dong Cho

Jin Youn Cho

Deep-submicron Placement Minimizing Crosstalk

John  Barker

Technology mapping is the final step of logic synthesis which consists of mapping an optimized technology
independent logic network representation into a circuit realization in a given technology. An important component
of the technology mapping problem is the identification of feasible library cells for the realization of the logic
operators in the logic tree. There are two main classes of such matching algorithms. Library-based matching
algorithms [1–4] require that all available physical components be represented explicitly in a pattern library.
Sections of the logic network are then matched against this pattern list for the identification of suitable
components. In contrast, cell generator-based matching techniques [6–8] accept feasibility constraints on the
complexity and quantity of physical components according to limits imposed by the target technology or the
capabilities of the cell generator. Hence, individual patterns are not stored in a library and are instead generated
as needed. In this paper, we present a new cell generator-based constructive matching algorithm. Because the
algorithm builds matched patterns incrementally, very large cell families can be accommodated using time and
space resources that are proportional to the size of the largest feasible cell pattern and not the size of the library
of patterns as would be the case for library-based approaches. Also, whereas existing cell generator-based
matching techniques combine the tasks of matching (identification) and covering (selection), constructive matching
provides more flexibility by not restricting the covering phase. Empirical results demonstrate the increased quality
of the technology-mapped circuits when larger cells are available.

Martin Lefebvre

Cliff Liem

Cell Generator-Based Technology Mapping
by Constructive Tree-Matching
and Dynamic Covering

Wolfgang  Porod

In this paper, we discuss the use of parallel discrete event simulation (PDES) algorithms for execution of hardwaremodels written in VHDL. We survey central event queue, conservative distributed and optimistic distributedPDES algorithms, and discuss aspects of the semantics of VHDL and VHDL-92 that affect the use of thesealgorithms in a VHDL simulator. Next, we describe an experiment performed as part of the Vsim Project at theUniversity of Adelaide, in which a simulation kernel using the central event queue algorithm was developed. Wepresent measurements taken from this kernel simulating some benchmark models. It appears that this technique,which is relatively simple to implement, is suitable for use on small scale multiprocessors (such as current desktopmultiprocessor workstations), simulating behavioral and register transfer level models. However, the degree ofuseful parallelism achievable on gate level models with this technique appears to be limited.

Peter J. Ashenden

Henry  Detmold

Wayne S. McKeen

Execution of VHDL Models Using Parallel DiscreteEvent Simulation Algorithms

In this paper, we present a novel fault detection and fault diagnosis technique for Field Programmable Gate Arrays (FPGAs). The cell is configured to implement a bijective function to simplify the testing of the whole cell array. The whole chip is partitioned into disjoint one-dimensional arrays of cells. For the lookup table (LUT), a fault may occur at the memory matrix, decoder, input or output lines. The input patterns can be easily generated with a k-bit binary counter, where k denotes the number of input lines of a configurable logic block (CLB). Theoretical proofs show that the resulting fault coverage is 100%. According to the characteristics of the bijective cell function, a novel built-in self-test structure is also proposed. Our BIST approaches have the advantages of requiring less hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, two diagnosis sessions are required. However, the maximum number of configurations is k + 4 for diagnosing a faulty CLB. The diagnosis complexity of our approach is also analyzed. Our results show that the time complexity is independent of the array size of the FPGA. In other words, we can make the FPGA array C-diagnosable.

Shyue-Kung Lu

Fu-Min Yeh

Jen-Sheng Shih

Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs

Jun-Dong Cho

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VLSI Design