Most algorithms for reconfigurable meshes (R-meshes) are based on the divide-and-conquer(DAC) strategy. Although the strategy per se does not require the subproblemsto be equal in size, existing DAC algorithms for R-meshes do divide the problemapproximately evenly. This paper demonstrates that dividing a problem evenly is notnecessarily a good way to decompose a problem. There are occasions on which anirregular decomposition scheme may be preferable. We take this approach and obtain anew sorting algorithm. Our sorting algorithm has several strengths: it is simple, scalable,and as broadcast-efficient as the best known result.

Ten H. Lai

Ming-Jye  Sheng

Sorting on Reconfigurable Meshes:An Irregular Decomposition Approach

The performance of Time Warp parallel discrete event simulators can be affected by thecancellation strategy used to send anti-messages. Under aggressive cancellation, antimessagegeneration occurs immediately after a straggler message is detected. In contrast,lazy cancellation delays the sending of anti-messages until forward processing from astraggler message confirms that the premature computation did indeed generate anincorrect message. Previous studies have shown that neither approach is clearly superiorto the other in all cases (even within the same application domain). Furthermore, nostrategy exists to make a priori determination of the more favorable cancellationstrategy. Most existing Time Warp systems merely provide a switch for the user to selectthe cancellation strategy employed. This paper explores the use of simulation timedecision procedures to select cancellation strategies. The approach is termed Dynamic Cancellation and it assigns the capability for selecting cancellation strategies to theLogical Processes (LPs) in a Time Warp simulation. Thus, within a single parallelsimulation both strategies may be employed by distinct LPs and even across thesimulation lifetime of an LP. Empirical analysis using several control strategies showthat dynamic cancellation always performs with the best static strategy and, in somecases, dynamic cancellation provides some nominal (5&#8211;10&#37;) performance gain over thebest static strategy.

Raghunandan  Rajan

Radharamanan  Radhakrishnan

Philip A. Wilsey

Dynamic Cancellation: Selecting Time WarpCancellation Strategies at Runtime

We investigate conservative parallel discrete event simulations for logical circuits on
shared-memory multiprocessors. For a first estimation of the possible speedup, we
extend the critical path analysis technique by partitioning strategies. To incorporate
overhead due to the management of data structures, we use a simulation on an ideal
parallel machine (PRAM). This simulation can be directly executed on the SB-PRAM
prototype, yielding both an implementation and a basis for data structure optimizations.
One of the major tools to achieve these optimizations is the SB-PRAM's
hardware support for parallel prefix operations. Our reimplementation of the PTHOR
program on the SB-PRAM yields substantially higher speedups than before.

Jörg Keller

Thomas Rauber

Bernd Rederlechner

Scalability Analysis for Conservative Simulation
of Logical Circuits

Azzedine  Boukerche

Guest Editorial

We develop an O(p log n) time algorithm to obtain optimal solutions to the p-pin n-netsingle channel performance-driven implementation selection problem in which eachmodule has at most two possible implementations (2-PDMIS). Although Her, Wangand Wong [1] have also developed an O(p log n) algorithm for this problem, experimentsindicate that our algorithm is twice as fast on small circuits and up to eleven timesas fast on larger circuits. We also develop an <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>O</mml:mi><mml:mo stretchy="false">(</mml:mo><mml:mi>p</mml:mi><mml:msup><mml:mi>n</mml:mi><mml:mrow><mml:mi>c</mml:mi><mml:mo>&#x2212;</mml:mo><mml:mn>1</mml:mn></mml:mrow></mml:msup><mml:mo stretchy="false">)</mml:mo></mml:mrow></mml:math> time algorithm for the c, c &#62; 1,channel version of the 2-PDMIS problem.

Edward Y. C. Cheng

Sartaj  Sahni

A Fast Algorithm for Performance-Driven Module Implementation Selection

This paper reports the development of the Cairo University Waveform Relaxation
(CUWORX) simulator. In order to accelerate the convergence of the waveform
relaxation (WR) in the presence of logic feedback, CUWORK is initialized via a logic
simulator. This logic initialization scheme is shown to be highly effective for digital
synchronous circuits. Additionally, this logic initialization scheme preserves fully the
multi-rate properties of the WR algorithm.

S. E.-D. Habib

G. J. Al-Karim

An Initialization Technique for the Waveform-Relaxation
Circuit Simulation

This paper reviews proposals for extensions to VHDL to support high-level modelingand places them within a taxonomy that describes the modeling requirements theyaddress. Many of the proposals focus on object-oriented extensions, whereas this paperargues that extension of VHDL to support high-level modeling requires a broaderreview. The paper presents a detailed discussion of issues to be considered in addinghigh-level modeling extensions to VHDL, including concurrency and communication,abstraction using entity interfaces, object-oriented data modeling, encapsulation, signalassignment semantics, shared variables, multiple inheritance, genericity and synthesis.Emphasis is placed on the importance of designing simple orthogonal semanticmechanisms that interact in well defined ways, and that integrate cleanly with existinglanguage features.

Peter J. Ashenden

Principles for Language Extensions to VHDL to Support High-Level Modeling

The use is made of the BJT transit frequency limit (fTL) dependence on the MOSFETparameters (L, Vth) to design BiCMOS digital circuits. The fTL relation is used inconjunction with the established BiCMOS gate delay models. It is shown that theminimum delay BiCMOS circuits driving the large capacitive load, can be designed atthe transit frequency limit with the reduced BJT AREA factor. The time delaycalculations are presented for a typical BiCMOS circuit and comparison is made withthe results simulated using SPICE.

A.  Srivastava

Influence of BJT Transit Frequency Limit Relationto MOSFET Parameters on the Switching Speedof BiCMOS Digital Circuits

In this paper, we present the concept of Field Programmable Memory Cell Arrays(FPMCAs) as the memory counterpart to Field Programmable Gate Arrays which haveproved their utility in design and rapid prototyping. Principles of dynamic reconfigurabilityusing programmable logic and programmable interconnect are incorporated intorandom access memories to achieve this flexibility. We first present the design of avariable width RAM (VaWiRAM) which is a simple example of a Field ProgrammableMemory Cell Array. The configuration of VaWiRAMs can be adjusted by setting a fewconfiguration pins on the memory chip. A VaWiRAM reconfigurable between widths 1 and <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>W</mml:mi><mml:mrow><mml:mi>max</mml:mi><mml:mo>&#x2061;</mml:mo></mml:mrow></mml:msub></mml:mrow></mml:math> can be constructed with the extra cost of <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>W</mml:mi><mml:mrow><mml:mi>max</mml:mi><mml:mo>&#x2061;</mml:mo></mml:mrow></mml:msub></mml:mrow></mml:math> &#8211; 1 pass gates, (<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>W</mml:mi><mml:mrow><mml:mi>max</mml:mi><mml:mo>&#x2061;</mml:mo></mml:mrow></mml:msub></mml:mrow></mml:math>/2) 2-to-1multiplexers, and <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mrow><mml:mo>&#x2308;</mml:mo><mml:mrow><mml:msub><mml:mrow><mml:mi>log</mml:mi><mml:mo>&#x2061;</mml:mo></mml:mrow><mml:mn>2</mml:mn></mml:msub><mml:mo stretchy="false">[</mml:mo><mml:msub><mml:mrow><mml:mi>log</mml:mi><mml:mo>&#x2061;</mml:mo></mml:mrow><mml:mn>2</mml:mn></mml:msub><mml:mo stretchy="false">(</mml:mo><mml:mi>k</mml:mi><mml:mo stretchy="false">)</mml:mo><mml:mtext>&#x2009;</mml:mtext><mml:mo>+</mml:mo><mml:mtext>&#x2009;</mml:mtext><mml:mn>1</mml:mn><mml:mo stretchy="false">]</mml:mo></mml:mrow><mml:mo>&#x02309;</mml:mo></mml:mrow></mml:mrow></mml:math> mode pins. A novel scheme to overlap the addresspins with mode control pins and achieve the mode control with only one extra pin is alsopresented. The paper discusses the architecture of the proposed VaWiRAMs in detail,analyzes the design tradeoffs and introduces the concept of FPMCAs.

Lizy Kurian John

Memory Chips with Adjustable Configurations

A novel architectural transformation for low power synthesis of inner productcomputational structures is presented. The proposed transformation reorders the sequenceof evaluation of the multiply-accumulate operations that form the inner products.Information related to both coefficients, which are statically determined, and data,which are dynamic, is used to drive the reordering of computation. The reordering ofcomputation reduces the switching activity at the inputs of the computational unitsbut inside them as well leading to power consumption reduction. Different classes ofalgorithms requiring inner product computation are identified and the problem ofcomputation reordering is formulated for each of them. The target architecture to whichthe proposed transformation applies is based on a power optimal memory organizationand is described in detail. Experimental results for several DSP algorithms show that theproposed transformation leads to significant savings in net switching activity and thus inpower consumption.

K.  Masselos

P.  Merakos

T.  Stouraitis

C. E. Goutis

Computation Reordering: A Novel Transformation for Low Power DSP Synthesis

Complex digital systems are often decomposed into architectures very early in the design
process. Unfortunately, traditional simulation based languages such as VHDL do not
allow the impact of these architectural decisions to be evaluated until a complete,
simulatable design of the system is available. After a complete design is available,
architectural errors are time-consuming and expensive to correct. However, there is an
alternative to simulation based techniques: formal analysis of abstract architectures at
the requirements level. This paper describes VSBEC'S approach for defining and analyzing
abstract architectures. VSBEC is a Larch interface language for VHDL that allows a
designer to specify the requirements of a VHDL entity using the canonical Larch
approach. VHDL structural architectures that instantiate VSPEC entities define abstract
architectures. These abstract architectures can be evaluated at the requirements level to
determine the impact of architectural decisions. This paper briefly introduces VSPEC
provides a formal definition of VSPEC abstract architectures and presents two examples
that illustrate the architectural definition capabilities of the language.

Phillip Baraona

Perry Alexander

Abstract Architecture Representation Using VSPEC

It is well known that standard cells have been widely used to implement VLSI circuits inthe automation of physical design. Since one major aim of a cell-based design is to minimizetotal layout area in a standard cell placement, the number of feedthrough cells willbe minimized to reduce total cell area in a standard cell placement. In this paper, first,we model a partitioning-based row assignment (PRA) problem to minimize the numberof feedthrough cells in a standard cell placement. Furthermore, an integer linear programming(ILP) approach is proposed to solve the PRA problem in a standard cellplacement. Finally, the ILP approach has been implemented and two standard-cell netlists,Primary 1 and Primary 2, have been tested by the proposed approach, Bose&#39;s approach[4] and an exhaustive search approach, respectively. The experimental results showthat the ILP approach obtains fewer feedthrough cells than Bose&#39;s approach in apartitioning-based standard cell placement.

Jin-Tai  Yan

An ILP Formulation for Minimizing the Numberof Feedthrough Cells in a Standard Cell Placement

We address the prblem of time-stationary control synthesis for pipelined data paths.Control synthesis system accepts scheduled control data flow graph with conditionalbranches which are produced by high level synthesis tools such as Sehwa [1] as inputspecification and generates a FSM controller. First a scheduled control/data flow graphis analyzed and the various states are identified. Overlapped states are grouped togetherto produce L groups where L is the pipeline latency. Next, state transitions are identifiedand a state table is generated. Finally, a highly optimized FSM controller isimplemented by performing horizontal partitioning and the corresponding staeencoding so as to minimize the total controller area. We compared our approach topublished work on FSM generation and optimization and the results indicate that ourmethod results in large savings in total controller area.

Jong Tae Kim

Fadi J. Kurdahi

Noh Byung Park

System-level Time-stationary Control Synthesis forPipelined Data Paths

Based on non-crossing relations, vertical constraint relations and net-geometry relationsin one T-type junction region, two kinds of routability crossing distributions areproposed to improve routing performance in one T-type junction region. For routabilitycrossing distribution in one T-type junction region, a routability-ordering graph is builtto decide a net ordering in <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>O</mml:mi><mml:mo stretchy="false">(</mml:mo><mml:msup><mml:mi>n</mml:mi><mml:mn>2</mml:mn></mml:msup><mml:mo stretchy="false">)</mml:mo></mml:mrow></mml:math> time. For routability quota crossing distribution in oneT-type junction region, if the number of net crossings in base channel is more than agiven quota, this net ordering in routability crossing distribution will be further adjustedto satisfy the quota requirement by using a net interchange operation in O(n) time. Forfloating pin assignment in one T-type junction region, global nets are assigned on theboundary between top channel and base channel by interleaving vacant pins in O(n)time according to a net ordering in routability crossing distribution.

Routability Crossing Distribution and Floating Pin Assignment for T-type Junction Region

A new method for implementing two-level logic circuits, which exhibit minimal power
dissipation, is introduced. Switching activity reduction of the logic network nodes is
achieved by adding extra input signals to specific gates. Employing the statistic properties
of the primary inputs, a new concept for grouping the input variables with similar
features is introduced. Appropriate input variables are chosen for reducing the
switching activity of a logic circuit. For that purpose, an efficient synthesis algorithm,
which generates the set of all groups of the variables and solves the minimum covering
problem for each group is developed. The comparison of the results, produced by the
proposed method, and those from ESPRESSO shows that a substantial power reduction
can be achieved.

G. Theodoridis

S. Theoharis

D. Soudris

C. Goutis

A New Method for Low Power Design of Two-Level Logic Circuits

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