We present in this paper an approach to designing partially strongly code-disjoint
(PSCD) CMOS circuits and checkers, considering transistor stuck-on faults in addition
to gate-level stuck-at faults. Our design-for-testability (DFT) technique requires only a
small number of extra transistors for monitoring abnormal static currents, coupled with
a simple clocking scheme, to detect the stuck-on faults concurrently. The DFT circuitry
not only can detect the faults in the functional circuit but also can detect or tolerate faults
in itself, making it a good candidate for checker design. Switch and circuit level
simulations were performed on a sample circuit, and a sample 4-out-of-8 code checker
chip using the proposed technique has been designed, fabricated, and tested, showing the
correctness of the method. Performance penalty is reduced by a novel BiCMOS checker
circuit.

Yeong-Ruey Shieh

Cheng-Wen Wu

Design of CMOS PSCD Circuits and Checkers for
Stuck-At and Stuck-On Faults

In this paper, a new optimization technique called SOFT(self-organizing fuzzy technique)
is proposed to solve the macro-cell placement problem. In SOFT, different criteria are
simultaneously accounted by a novel fuzzy gain function which models expert knowledge
to control the optimization process. The presented procedure is an adaptation of
Kohonen's self-organization algorithm which is well suited for implementation on
massively parallel architecture for fast computing. The MCNC benchmark examples are
presented to verify the performance and feasibility of SOFT. Comparisons are made
with the Hopfield network, SOAP and TimberWolf MC5.6. Experiments show that the
proposed method yields an average of 17% improvement in total wire length compared
with previous methods. Large size problems with 225 and 1024 arbitrarily-sized macrocells
are also presented.

Ray-I Chang

Pei-Yung Hsiao

Macro-Cell Placement for Custom-Chip Design Using Self-Organizing Fuzzy Technique

Using the finite element method, we investigate device applications of lateral resonant tunneling
structures which consist of a transmission channel with attached resonators. Such
structure exhibits resonance-antiresonance transmission features which may be engineered to
achieve desired device properties.
We show that the valley current can be reduced in such 2D lateral resonant tunneling
devices, resulting in an improved current peak-to-valley ratio.

Zhi-An Shao

Wolfgang Porod

Craig S. Lent

2D Finite Element Method Simulation of Lateral Resonant Tunneling Devices

Given a set of terminals on the plane <mml:math id="E1" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>N</mml:mi><mml:mo>=</mml:mo><mml:mrow><mml:mo>{</mml:mo><mml:mrow><mml:mi>s</mml:mi><mml:mo>,</mml:mo><mml:msub><mml:mi>ν</mml:mi><mml:mn>1</mml:mn></mml:msub><mml:mo>,</mml:mo><mml:mo>…</mml:mo><mml:mo>,</mml:mo><mml:msub><mml:mi>ν</mml:mi><mml:mi>n</mml:mi></mml:msub></mml:mrow><mml:mo>}</mml:mo></mml:mrow></mml:math>, with a source terminal s, a
Rectilinear Distance-Preserving Tree (RDPT) T(V, E) is defined as a tree rooted at s,
connecting all terminals in N. An RDPT has the property that the length of every source
to sink path is equal to the rectilinear distance between that source and sink. A Min-
Cost Rectilinear Distance-Preserving Tree (MRDPT) minimizes the total wire length
while maintaining minimal source to sink linear delay, making it suitable for high
performance interconnect applications.This paper studies problems in the construction of RDPTs, including the following
contributions. A new exact algorithm for a restricted version of the problem in one
quadrant with O<mml:math id="E2" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mo>(</mml:mo><mml:mrow><mml:msup><mml:mi>n</mml:mi><mml:mn>2</mml:mn></mml:msup></mml:mrow><mml:mo>)</mml:mo></mml:mrow></mml:math> time complexity is proposed. A novel heuristic algorithm, which
uses optimally solvable sub-problems, is proposed for the problem in a single quadrant.
The average and worst-case time complexity for the proposed heuristic algorithm are O<mml:math id="E3" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mo>(</mml:mo><mml:mrow><mml:msup><mml:mi>n</mml:mi><mml:mrow><mml:mrow><mml:mn>3</mml:mn><mml:mo>/</mml:mo><mml:mn>2</mml:mn></mml:mrow></mml:mrow></mml:msup></mml:mrow><mml:mo>)</mml:mo></mml:mrow></mml:math> and O<mml:math id="E4" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mo>(</mml:mo><mml:mrow><mml:msup><mml:mi>n</mml:mi><mml:mn>3</mml:mn></mml:msup></mml:mrow><mml:mo>)</mml:mo></mml:mrow></mml:math>, respectively. A 2-approximation of the quadrant merging problem is proposed. The proposed algorithm has time complexity <mml:math id="E5" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>O</mml:mi><mml:mrow><mml:mo>(</mml:mo><mml:mrow><mml:msup><mml:mi>α</mml:mi><mml:mn>2</mml:mn></mml:msup><mml:mi>T</mml:mi><mml:mrow><mml:mo>(</mml:mo><mml:mi>n</mml:mi><mml:mo>)</mml:mo></mml:mrow><mml:mo>+</mml:mo><mml:msup><mml:mi>α</mml:mi><mml:mn>3</mml:mn></mml:msup></mml:mrow><mml:mo>)</mml:mo></mml:mrow></mml:math> for any constant
α &gt; 1, where T(n) is the time complexity of the solution of the RDPT problem on one
quadrant. This result improves over the best previous quadrant merging solution which
has <mml:math id="E6" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>O</mml:mi><mml:mrow><mml:mo>(</mml:mo><mml:mrow><mml:msup><mml:mi>n</mml:mi><mml:mn>2</mml:mn></mml:msup><mml:mi>T</mml:mi><mml:mrow><mml:mo>(</mml:mo><mml:mi>n</mml:mi><mml:mo>)</mml:mo></mml:mrow><mml:mo>+</mml:mo><mml:msup><mml:mi>n</mml:mi><mml:mn>3</mml:mn></mml:msup></mml:mrow><mml:mo>)</mml:mo></mml:mrow></mml:math> time complexity.We test our algorithms on randomly uniform point sets and compare our heuristic
RDPT construction against a Minimum Cost Rectilinear Steiner (MRST) tree
approximation algorithm. Our results show that RDPTs are competitive with Steiner
trees in total wire-length when the number of terminals is less than 32. This result makes
RDPTs suitable for VLSI routing applications. We also compare our algorithm to the
Rao-Shor RDPT approximation algorithm obtaining improvements of up to 10% in
total wirelength. These comparisons show that the algorithms proposed herein produce
promising results.

Gustavo E. Téllez

Majid Sarrafzadeh

On Rectilinear Distance-Preserving Trees

The generalized tunneling formula with the simple model for the broadening in the contactsgives surprisingly good results for the majority of RTD structures. It is just as fast as thestandard coherent tunneling simulators and much more versatile. It is easily generalized tomulti-band and multidimensional models. The multi-band generalization of the theory and theeffect of the optical potential are described.

R.  Lake

G.  Klimeck

R. C. Bowen

D.  Jovanovic

P.  Sotirelis

W. R. Frensley

A Generalized Tunneling Formula for Quantum Device Modeling

Although impact ionization feedback is recognized as an important current multiplicationmechanism, its importance as a carrier heating mechanism has been largelyoverlooked. This work emphasizes the inclusion of impact ionization feedback in MonteCarlo device simulations, and its implications for carrier heating in sub-micron CMOSand EEPROM technologies.

Jeff D. Bude

Monte Carlo Simulations of Impact Ionization Feedback in MOSFET Structures

Every knock-knee layout is four-layer wirable. However, there are knock-knee layouts
that cannot be wired in less than four layers. While it is easy to determine whether a
knock-knee layout is one-layer wirable or two-layer wirable, the problem of determining
three-layer wirability of knock-knee layouts is NP-complete. A knock-knee layout may
be stretched vertically (horizontally) by introducing empty rows (columns) so that it can
be wired in fewer than four layers. In this paper we discuss two different types of
stretching schemes. It is known that under these two stretching schemes, any knock-knee
layout is three-layer wirable by stretching it up to (4/3) of the knock-knee layout
area (upper bound). We show that there are knock-knee layouts that when stretched
and wired in three layers under scheme I (II) require at least 1.2 (1.07563) of the original
layout area. Our lower bound for the area increase factor can be used to guide the
search for effective stretching-based dynamic programming three-layer wiring algorithms
similar to the one presented in [8].

Teofilo F. Gonzalez

Si-Qing Zheng

On Ensuring Multilayer Wirability by Stretching Layouts

The complex recess and gate shape of modem compound FETs greatly affect the device parasiticsand therefore impose the need for proper description of the device geometry and surfaceconditions in any practical device simulations. In this paper we describe a new Monte Carlo(MC) module incorporated in our Heterojunction 2D Finite element FET simulator H2F [1].The module combines realistic quadrilateral finite-element description of the device geometrywith realistic particle simulation of the non-equilibrium hot carrier transport in shortrecess gate compound FETs. A Single Programme Multiple Data (SPMD) parallel approachmakes it possible to use our MC simulator for practical design work, generating the necessaryI-V characteristics in parallel. The capabilities of the finite element MC module are illustratedin example simulations of a 200nm pseudomorphic HEMT fabricated in the NanoelectronicsResearch Centre of Glasgow University.

S.  Babiker

A.  Asenov

J. R. Barker

S. P. Beaumont

Quadrilateral Finite Element Monte Carlo Simulation of Complex Shape Compound FETs

Electron transport was studied in an open square quantum dot with a dimension typical
for current experiments. A numerical analysis of the probability density distribution
inside the dot was performed which enabled us to unambiguously map the resonant states
which dominate the conductance of the structure. It was shown that, despite of the
presence of dot openings, transport through the dot is effectively mediated by just a few
(or even a single) eigenstates of the corresponding closed structure. In a single-mode
regime in the leads, the broadening of the resonant levels is typically smaller than the
mean energy level spacing, Δ. On the contrary, in the many-mode regime this broadening
typically exceeds Δ and has an irregular, essentially non-Lorentzian, character. It was
demonstrated that in the latter case eigenlevel spacing statistics of the corresponding
closed system are not relevant to the averaged transport properties of the dot. This
conclusion seems to have a number of experimental as well as numerical verifications.

I. V. Zozoulenko

K.-F. Berggren

Quantum Transport in Open Nanostructures

In self-checking systems, checkers usually do not receive all code words during normal
operation. Missing code words may prevent a checker from achieving the totally self-checking
property. The paper presents a novel approach to the design of embedded
parity and two-rail checkers that allows a checker to receive all code words irrespective of
the set of code words that is provided by the functional circuit. A checker gets all code
words by an LFSR while at the same time it monitors the output of the functional circuit.
Additionally, the LFSR is able to capture the error patterns of noncode words. Captured
error patterns will be modified since they will cycle through the LFSR. Thus, noncode
words that are not detected due to undetected checker faults can be detected in later
instances of time. The proposed method can be extended to the design of checkers for
linear codes.

Steffen Tarnick

Embedded Parity and Two-Rail TSC Checkers with
Error-Memorizing Capability

In FPGAs the routing resources are fixed and their usage is constrained by the locationof antifuses. In addition, the antifuses affect the layout performance significantly,depending on the technology. Hence, simplistic placement level assumptions turn out tobe grossly inadequate in predicting the timing and wirability behavior of a layout.There is a need, therefore, for a layout technique which changes the layout at placementlevel based on accurate post-layout timing analysis and net wirability. In this paper weconsider such a wirability and performance driven layout flow for row-based FPGAs.Timing information from a post-layout timing analyzer and wirability informationfrom global and channel routers are used by an incremental placer to effectively perturbthe placement. A large improvement (up to 29&#37;) in timing, has been obtained(compared to non-iterative FPGA layout) for a set of industrial designs and benchmarkexamples.

Sudip  Nag

Kaushik  Roy

Performance and Wirability Driven Layout for Row-Based FPGAs

It is argued that the Pauli master equation can be used to simulate electron transport invery small electronic devices under steady-state conditions. Written in a basis of suitablewavefunctions and with the appropriate open boundary conditions, this equationremoves some of the approximations which render the Boltzmann equationunsatisfactory at small length-scales. The main problems consist in describing theinteraction of the system with the reservoirs and in assessing the range of validity of theequation: Only devices smaller than the size of the electron wavepackets injected fromthe contacts can be handled. Two one-dimensional examples solved by a simple MonteCarlo technique are presented.

M. V. Fischetti

Theory of Electron Transport in Small SemiconductorDevices Using the Pauli Master Equation

In this paper we propose a structure dependent method for the systematic design of a self-checking
circuit which is well adapted to the fault model of single gate faults and which
can be used in test mode.According to the fault model considered, maximal groups of independent and
unidirectionally independent outputs of an arbitrarily given combinational circuit are
determined. A parity bit is added to every group of independent outputs. A few
additional outputs are added to every group of unidirectionally independent outputs. In
the error free case, these groups of unidirectional independent outputs together with their
corresponding additional outputs are elements of a unidirectional error detecting code;
for example, a Berger code or an r-out-of-s code.It is demonstrated how the pairs of (unidirectionally) independent outputs of a given
circuit can be determined. A simple heuristic solution for this problem based on a
modified circuit graph is also given.The maximal classes of (unidirectionally) independent outputs can be computed as
cliques of a dependency graph where the nodes of the graph are the outputs of the circuit.
The applicability of the proposed method is demonstrated for the MCNC benchmarks
circuits.

A. Morosow

V. V. Saposhnikov

Vl. V. Saposhnikov

M. Goessel

Self-Checking Combinational Circuits with Unidirectionally
Independent Outputs

We describe a newly developed parallel three-dimensional semiconductor device simulator.The program utilizes the message passing architecture and has been developed on a networkof workstations. Two iterative algorithms to solve the nonlinear semiconductor device equationsare presented. The algorithms are tested by simulating a three-dimensional MOSFETstructure. A near-ideal speedup for the distributed algorithms has been obtained for Poisson’sequation.

Mei-Kei  Ieong

Ting-Wei  Tang

Distributed Algorithms for Three-dimensionalSemiconductor Device Simulations

In this paper we present an approach for combining on-line concurrent checking (CC)
with off-line built-in self-test (BIST). We will show that a reduction of an aliasing
probability can be obtained for manufacturing testing by monitoring the output of a
concurrent checker and a reduction of a probability of not detecting an error in the
computing mode can be obtained by a short periodic BIST. We will present a technique
for optimal selection of error-detecting codes for combined on-line CC and off-line
space-time compression of test responses for BIST and estimate probabilities of not
detecting an error for the approach based on integrating CC and BIST. We also present a
technique for on-line error-detection in space-time compressors of test responses for
BIST.

Mark G. Karpovsky

Integrated On-Line and Off-Line Error Detection
Mechanisms in the Coding Theory Framework

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