We describe a new and efficient method for numerical study of the dynamics and statistics of
single-electron systems presenting arbitrary combinations of small tunnel junctions, capacitances,
and voltage sources. The method is based on the numerical solution of a master equation
describing the time evolution of the probabilities of the electric charge states of the
system, with iterative refining of the operational set of states. The method is able to describe
very small deviations from the “classical” behavior of a system, due to finite speed of applied
signals, thermal activation, and macroscopic quantum tunneling of charge (cotunneling). As
an illustration, we briefly study the leakage rate in single-electron traps and the accuracy of
several devices (turnstile, pump, and a hybrid circuit) suitable as standards of dc current.

L. R. C. Fonseca

A. N. Korotkov

K. K. Likharev

SENECA: a New Program for the Analysis of Single-Electron Devices

Fault sets that accurately describe physical failures are required for efficient pattern
generation and fault coverage evaluation. The fault model presented in this paper
uniquely describes all structural changes in the transistor net list that can be caused by
spot defects, including bridging faults that connect more than two nets, break faults that
break a net into more than two parts, and compound faults. The developed analysis
method extracts the comprehensive set of realistic faults from the layout of CMOS ICs
and for each fault computes the probability of occurrence. The results obtained by the
tool REFLEX show that bridging faults connecting more than two nets account for a
significant portion of all faults and cannot be neglected.

Gerald Spiegel

Albrecht P. Stroele

Realistic Fault Modeling and Extraction of Multiple Bridging and Break Faults

Monte Carlo simulations of uniform silicon nMOSFET inversion layers have been performed.
Excellent agreement between the simulated and experimental transport characteristics
has been observed in the region of strong inversion at both 300K and 77K. The
contribution to the effective mobility due to individual subbands has been analyzed and qualitatively
explained.

W.-K. Shih

S. Jallepalli

C.-F. Yeap

M. Rashed

C. M. Maziar

A. F. Tasch

A Monte Carlo Study of Electron Transport in Silicon nMOSFET Inversion Layers

The nanoelectronic modeling (NEMO) program is the result of a three-yeardevelopment effort involving four universities and the former Corporate Researchand Development Laboratory of Texas Instruments, now Applied Research Laboratory,Raytheon TI Systems, to create a comprehensive quantum device modeling toolfor layered semiconductor structures. Based on the non-equilibrium Green functionformalism, it includes the effects of quantum charging, bandstructure and incoherentscattering from alloy disorder, interface roughness, acoustic phonons, and polar opticalphonons. NEMO addresses the diverse needs of two different types of users: (i) theengineer/experimentalist who desires a black-box design tool and (ii) the theorist who isinterested in a detailed investigation of the physics. A collection of models trade offphysical content with speed and memory requirements. Access to this comprehensivetheoretical framework is accommodated by a Graphical User Interface (GUI) thatfacilitates device prototyping and in situ data analysis. We describe a hierarchicalsoftware design that allows rapid incorporation of theory enhancements whilemaintaining a user-friendly GUI, thus satisfying the conflicting criteria of ease of useand ease of development. The theory and GUI modules share data structures that definethe device structure, material parameters, and simulation parameters. These datastructures may contain general data such as integer and real numbers, option lists,vectors, matrices and the labels for both batch and GUI operation. NEMO generatesthe corresponding GUI elements at run-time for display and entry of these datastructures.

Gerhard  Klimeck

Dan  Blanks

Roger  Lake

R. Chris Bowen

Chenjing L. Fernando

Manhua  Leng

 William R. Frensley

Dejan  Jovanovic

Paul  Sotirelis

Writing Research Software in a Large Group for the NEMO Project

A technique for designing totally self-checking (TSC) FCMOS (Fully Complementary
MOS) designs for multiple faults is presented in this paper. The existing techniques for
self checking design consider only single faults, and suffer from high silicon area
overhead. The multiple faults considered in this paper are multiple breaks, multiple
transistors stuck-offs and multiple transistors stuck-ons. Starting from FCMOS design,
small modifications (addition of two-weak transistors) make the original circuit totally
self-checking. Experiemntal results show the overhead, delay and power consumption
for the proposed technique. This paper also presents a technique for designing
multistage TSC FCMOS circuits.

Fadi Busaba

Parag K. Lala

Alvernon Walker

On Self-Checking Design of CMOS Circuits for Multiple Faults

An important class of biological molecules-proteins called ionic channels&#8211;conductions (like Na+, K+, Cl-) through a narrow tunnel of fixed charge (&#8216;doping&#8217;). Ionic channels are the main pathway by which substances move into cells and so are of greatbiological and medical importance: a substantial fraction of all drugs used by physicians act on channels. Channels can be studied in the tradition of computational electronics. Drift diffusion equations form an adequate model of IV relations of 6 different channel proteins in &#820; 10 solutions over &#177;150 mV. Ionic channels can also be studied with thepowerful techniques of molecular biology. Atoms can be modified one at a time and the location of every atom can be determined. Ionic channels are natural nanotubes that can be controlled more precisely and easily than physical nanostructures but biologists need help if realistic simulations are to be done atomic detail.

Bob  Eisenberg

Ionic Channels in Biological Membranes: NaturalNanotubes Described by the Drift-Diffusion Equations

Recent scanning tunneling microscopy (STM) studies on the (111) faces of noble metals have
directly imaged electronic surface-confined states and dramatic standing-wave patterns have
been observed 1,2]. We solve for the local density of electronic states in these “leaky” quantum
corral confinement structures using a coherent elastic scattering theory. We seek solutions
of the two-dimensional Schrödinger equation compatible with non-reflecting boundary
conditions which asymptotically satisfy the Sommerfeld radiation condition [11,14]. The
large matrices generated by the discretization of realistic quantum corral structures require the
use of sparse matrix methods. In addition, a parallel finite element solution was undertaken
using the message passing interface standard (MPI) and the Portable, Extensible, Toolkit for
Scientific Computation (PETSc) [5] for an efficient computational solution on both distributed
and shared memory architectures. Our calculations reveal excellent agreement with the
reported experimental dl/dV STM data.

Henry K. Harbury

Wolfgang Porod

Parallel Computation for Electronic Waves in Quantum Corrals

We have suggested a novel family of wireless single-electron digital devices, based on the
parametric excitation principle. The basic cell is a short array of small conducting islands separated
by tunnel barriers with relatively low capacitance and conductance. External rf (clock)
field creates conditions for spontaneous breaking of the charge symmetry of the cell. The
symmetry may be broken by the signal field provided by the neighboring cell(s). This mode
ensures robust operation of the parametron-based logic circuits. Moreover, these devices may
be reversible, dissipating energy well below kBT 1n2 per logic operation.

Konstantin K. Likharev

Alexander N. Korotkov

Single-Electron Parametron

Molecular wires have several promising features, that would appear to make them ideal
for advanced interconnects in nanoscale electronic devices. We discuss several aspects of
the linear and nonlinear conductance of molecular wire interconnects. Topics include
energy dependence of molecular conductance, resonant tunneling behavior, control of
conductance by molecular structure and geometry, length dependence including the
tunneling regime energetics. Design rules using molecular interconnects will differ
substantially from those with more standard, lithographically structured silicon
interconnects. In particular, the dissipation mechanisms will differ, both tunneling and
ballistic regimes should be available, coulomb blockade and staircase behavior will be
observed (but under differing conditions) and fabrication of gate electrodes is a challenge.

Mathieu Kemp

Vladimiro Mujica

Adrian Roitberg

Mark A. Ratner

Molecular Wire Interconnects: Chemical Structural Control, Resonant Tunneling and
Length Dependence

A common technique widely used to achieve fault tolerance in systolic arrays consists inincorporating in the array additional processing elements (PEs) and extra bypass links.Given a sufficient number of PEs and a large enough set of bypass links, it might seemthat the array can easily tolerate a large number of faults provided they do not occur inconsecutive locations. It is not always the case as shown in this paper. In fact, certainfault patterns exist and may occur which would prevent any kind of restructuring of thearay, thus making the structure unusable. For a given set of bypass links from each PEin the array, it is possible to identify such fault patterns which will prevent anyreconfiguration. In this paper, we identify the class of fault patterns that arecatastrophic for linear systolic arrays, examine their characteristics, and describe amethod for constructing such fault patterns.

Vincenzo  Acciaro

Amiya  Nayak

Characterization of Catastrophic Faults in Reconfigurable Systolic Arrays

A new type of ultradense logic based on single-electron tunneling is considered. The basic
element is a short chain of conducting islands which shows bistable polarization and affects
the polarization of neighboring chains. The power is supplied by alternating electric field.

Possible Wireless Single-Electron Logic Biased by Electric Field

Circuits of VLSI complexity are designed using modules such as adders, multipliers,
register files, memories, multiplexers, and busses. During the high-level design of such a
circuit, it is important to be able to consider several alternative designs and compare
them on counts of area, performance, and testability. While tools exist for area and
delay estimation of module-level circuits, most of the testability analysis tools work on
gate-level descriptions of the circuit. Thus an expensive operation of flattening the
circuit becomes necessary to carry out testability analysis. In this paper, we describe a
time and space-efficient technique for evaluating the well known SCOAP testability
measure of a circuit from its hierarchical description with two or more levels of
hierarchy. We introduce the notion of SCOAP Expression Diagrams for functional
modules, which can be precomputed and stored as part of the module data base. Our
hierarchical testability analysis program, HISCOAP, reads the SCOAP expression
diagrams for the modules used in the circuit, and evaluates the SCOAP measure in a
systematic manner. The program has been implemented on a Sun/SPARC workstation,
and we present results on several benchmark circuits, both combinational and
sequential. We show that our algorithm also has a straightforward parallel realization.

C. P. Ravikumar

H. Joshi

SCOAP-based Testability Analysis from Hierarchical Netlists

Within a correlation-function (CF) formalism, the kinetic coefficientsof charge carriers in semiconductors are studied under different conditions. For the case of linear response in equilibrium, thetransitions from the non-degenerate to the degenerate regimes as wellas from ballistic to diffusive conditions are discussed within ananalytical model. Generalizing the method to high-field transport innondegenerate semiconductors, the CFs are determined by Monte Carlo (MC) calculations for bulk silicon from which the appropriate thermalconductivity has been
obtained and included into the hydrodynamic code HEIELDS. For an n+nn+ submicron structure the temperatureand velocity profiles of the carriers have been calculated with HFIELDS.

A. Greiner

L. Varani

L. Reggiani

M. C. Vecchi

T. Kuhn

P. Golinelli

Carrier Thermal Conductivity: Analysis and Application to Submicron-Device Simulation

Carl L. Gardner

Guest Editorial

Jun-Dong  Cho

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